* [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation
@ 2013-12-02 16:43 Liu, Jinsong
2013-12-02 17:39 ` Paolo Bonzini
2013-12-05 16:08 ` Paolo Bonzini
0 siblings, 2 replies; 6+ messages in thread
From: Liu, Jinsong @ 2013-12-02 16:43 UTC (permalink / raw)
To: Paolo Bonzini, Gleb Natapov, qemu-devel@nongnu.org, kvm
Cc: haoxudong.hao@gmail.com
[-- Attachment #1: Type: text/plain, Size: 2313 bytes --]
>From fbfa537f690eca139a96c6b2636ab5130bf57716 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Fri, 29 Nov 2013 01:27:00 +0800
Subject: [PATCH 1/4] X86: Intel MPX definiation
Signed-off-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
---
arch/x86/include/asm/cpufeature.h | 2 ++
arch/x86/include/asm/xsave.h | 5 ++++-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 89270b4..1b00b01 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -216,6 +216,7 @@
#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
@@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32];
#define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2)
#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
+#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 0415cda..d3e3ea5 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -9,6 +9,8 @@
#define XSTATE_FP 0x1
#define XSTATE_SSE 0x2
#define XSTATE_YMM 0x4
+#define XSTATE_BNDREGS 0x8
+#define XSTATE_BNDCSR 0x10
#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
@@ -23,7 +25,8 @@
/*
* These are the features that the OS can handle currently.
*/
-#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
+#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | \
+ XSTATE_BNDREGS | XSTATE_BNDCSR)
#ifdef CONFIG_X86_64
#define REX_PREFIX "0x48, "
--
1.7.1
[-- Attachment #2: 0001-X86-Intel-MPX-definiation.patch --]
[-- Type: application/octet-stream, Size: 2256 bytes --]
From fbfa537f690eca139a96c6b2636ab5130bf57716 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Fri, 29 Nov 2013 01:27:00 +0800
Subject: [PATCH 1/4] X86: Intel MPX definiation
Signed-off-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
---
arch/x86/include/asm/cpufeature.h | 2 ++
arch/x86/include/asm/xsave.h | 5 ++++-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 89270b4..1b00b01 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -216,6 +216,7 @@
#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
@@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32];
#define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2)
#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
+#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 0415cda..d3e3ea5 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -9,6 +9,8 @@
#define XSTATE_FP 0x1
#define XSTATE_SSE 0x2
#define XSTATE_YMM 0x4
+#define XSTATE_BNDREGS 0x8
+#define XSTATE_BNDCSR 0x10
#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
@@ -23,7 +25,8 @@
/*
* These are the features that the OS can handle currently.
*/
-#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
+#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | \
+ XSTATE_BNDREGS | XSTATE_BNDCSR)
#ifdef CONFIG_X86_64
#define REX_PREFIX "0x48, "
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation
2013-12-02 16:43 [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation Liu, Jinsong
@ 2013-12-02 17:39 ` Paolo Bonzini
2013-12-05 16:08 ` Paolo Bonzini
1 sibling, 0 replies; 6+ messages in thread
From: Paolo Bonzini @ 2013-12-02 17:39 UTC (permalink / raw)
To: Liu, Jinsong
Cc: haoxudong.hao@gmail.com, qemu-devel@nongnu.org, Gleb Natapov, kvm
Il 02/12/2013 17:43, Liu, Jinsong ha scritto:
> From fbfa537f690eca139a96c6b2636ab5130bf57716 Mon Sep 17 00:00:00 2001
> From: Liu Jinsong <jinsong.liu@intel.com>
> Date: Fri, 29 Nov 2013 01:27:00 +0800
> Subject: [PATCH 1/4] X86: Intel MPX definiation
>
> Signed-off-by: Xudong Hao <xudong.hao@intel.com>
> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
> ---
> arch/x86/include/asm/cpufeature.h | 2 ++
> arch/x86/include/asm/xsave.h | 5 ++++-
> 2 files changed, 6 insertions(+), 1 deletions(-)
>
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 89270b4..1b00b01 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -216,6 +216,7 @@
> #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
> #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
> #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
> +#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
> #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
> #define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
> #define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
> @@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32];
> #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2)
> #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
> #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
> +#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
> #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
> #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
>
> diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
> index 0415cda..d3e3ea5 100644
> --- a/arch/x86/include/asm/xsave.h
> +++ b/arch/x86/include/asm/xsave.h
> @@ -9,6 +9,8 @@
> #define XSTATE_FP 0x1
> #define XSTATE_SSE 0x2
> #define XSTATE_YMM 0x4
> +#define XSTATE_BNDREGS 0x8
> +#define XSTATE_BNDCSR 0x10
>
> #define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
>
> @@ -23,7 +25,8 @@
> /*
> * These are the features that the OS can handle currently.
> */
> -#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
> +#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | \
> + XSTATE_BNDREGS | XSTATE_BNDCSR)
>
> #ifdef CONFIG_X86_64
> #define REX_PREFIX "0x48, "
>
The patches look good. Please include a cover letter (patch 0/n) next
time, and detail the changes from previous submissions.
It would also be nice to have support of the new feature for nested VMX
as well (including kvm-unit-tests coverage).
Paolo
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation
2013-12-02 16:43 [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation Liu, Jinsong
2013-12-02 17:39 ` Paolo Bonzini
@ 2013-12-05 16:08 ` Paolo Bonzini
2013-12-05 22:59 ` H. Peter Anvin
1 sibling, 1 reply; 6+ messages in thread
From: Paolo Bonzini @ 2013-12-05 16:08 UTC (permalink / raw)
To: Liu, Jinsong
Cc: kvm, Gleb Natapov, qemu-devel@nongnu.org, Ingo Molnar,
haoxudong.hao@gmail.com, H. Peter Anvin, Thomas Gleixner
Il 02/12/2013 17:43, Liu, Jinsong ha scritto:
> From fbfa537f690eca139a96c6b2636ab5130bf57716 Mon Sep 17 00:00:00 2001
> From: Liu Jinsong <jinsong.liu@intel.com>
> Date: Fri, 29 Nov 2013 01:27:00 +0800
> Subject: [PATCH 1/4] X86: Intel MPX definiation
>
> Signed-off-by: Xudong Hao <xudong.hao@intel.com>
> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
> ---
> arch/x86/include/asm/cpufeature.h | 2 ++
> arch/x86/include/asm/xsave.h | 5 ++++-
> 2 files changed, 6 insertions(+), 1 deletions(-)
>
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 89270b4..1b00b01 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -216,6 +216,7 @@
> #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
> #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
> #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
> +#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
> #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
> #define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
> #define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
> @@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32];
> #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2)
> #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
> #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
> +#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
> #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
> #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
>
> diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
> index 0415cda..d3e3ea5 100644
> --- a/arch/x86/include/asm/xsave.h
> +++ b/arch/x86/include/asm/xsave.h
> @@ -9,6 +9,8 @@
> #define XSTATE_FP 0x1
> #define XSTATE_SSE 0x2
> #define XSTATE_YMM 0x4
> +#define XSTATE_BNDREGS 0x8
> +#define XSTATE_BNDCSR 0x10
>
> #define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
>
> @@ -23,7 +25,8 @@
> /*
> * These are the features that the OS can handle currently.
> */
> -#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
> +#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | \
> + XSTATE_BNDREGS | XSTATE_BNDCSR)
>
> #ifdef CONFIG_X86_64
> #define REX_PREFIX "0x48, "
>
hpa/Ingo/Thomas, can you give your Acked-by for this patch?
I'm not sure of the consequences of changing XCNTXT_MASK. This series
(which was submitted with the wrong threading) wants it so that KVM can
use fpu_save_init and fpu_restore_checking to save and restore the MPX
state of the guest.
Paolo
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation
2013-12-05 16:08 ` Paolo Bonzini
@ 2013-12-05 22:59 ` H. Peter Anvin
2013-12-06 8:22 ` Paolo Bonzini
0 siblings, 1 reply; 6+ messages in thread
From: H. Peter Anvin @ 2013-12-05 22:59 UTC (permalink / raw)
To: Paolo Bonzini, Liu, Jinsong
Cc: kvm, Gleb Natapov, Xudong Hao, qemu-devel@nongnu.org, Ingo Molnar,
Thomas Gleixner, Ren, Qiaowei
On 12/05/2013 08:08 AM, Paolo Bonzini wrote:
> Il 02/12/2013 17:43, Liu, Jinsong ha scritto:
>> From fbfa537f690eca139a96c6b2636ab5130bf57716 Mon Sep 17 00:00:00 2001
>> From: Liu Jinsong <jinsong.liu@intel.com>
>> Date: Fri, 29 Nov 2013 01:27:00 +0800
>> Subject: [PATCH 1/4] X86: Intel MPX definiation
>>
>> Signed-off-by: Xudong Hao <xudong.hao@intel.com>
>> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
>> ---
>> arch/x86/include/asm/cpufeature.h | 2 ++
>> arch/x86/include/asm/xsave.h | 5 ++++-
>> 2 files changed, 6 insertions(+), 1 deletions(-)
>>
>
> hpa/Ingo/Thomas, can you give your Acked-by for this patch?
>
> I'm not sure of the consequences of changing XCNTXT_MASK. This series
> (which was submitted with the wrong threading) wants it so that KVM can
> use fpu_save_init and fpu_restore_checking to save and restore the MPX
> state of the guest.
>
Hi, I'm currently reviewing internally another set of patches for MPX
support which would at least in part conflict with these. I don't see
the rest of the series -- where was it posted?
Either way:
1. asm/cpufeatures.h patches should always be separate, as we put those
into a special branch into the -tip tree since they touch so many other
things.
2. Enabling MPX is only safe with XSTATE_EAGER, which Qiaowei's patchset
has done correctly.
-hpa
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation
2013-12-05 22:59 ` H. Peter Anvin
@ 2013-12-06 8:22 ` Paolo Bonzini
0 siblings, 0 replies; 6+ messages in thread
From: Paolo Bonzini @ 2013-12-06 8:22 UTC (permalink / raw)
To: H. Peter Anvin
Cc: Liu, Jinsong, kvm, Gleb Natapov, Xudong Hao,
qemu-devel@nongnu.org, Ingo Molnar, Thomas Gleixner, Ren, Qiaowei
Il 05/12/2013 23:59, H. Peter Anvin ha scritto:
> Hi, I'm currently reviewing internally another set of patches for MPX
> support which would at least in part conflict with these. I don't see
> the rest of the series -- where was it posted?
It was posted to kvm-devel and not threaded. :(
Paolo
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation
@ 2013-11-29 13:41 Liu, Jinsong
0 siblings, 0 replies; 6+ messages in thread
From: Liu, Jinsong @ 2013-11-29 13:41 UTC (permalink / raw)
To: Paolo Bonzini, Gleb Natapov, qemu-devel@nongnu.org, kvm
Cc: haoxudong.hao@gmail.com
[-- Attachment #1: Type: text/plain, Size: 2311 bytes --]
>From 3a1a011100b38a275d8c95468c12c483e316bb15 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Fri, 29 Nov 2013 01:27:00 +0800
Subject: [PATCH 1/4] X86: Intel MPX definiation
Signed-off-by: Xudong Hao <xudong.hao@intel.com>
Reviewed-by: Liu Jinsong <jinsong.liu@intel.com>
---
arch/x86/include/asm/cpufeature.h | 2 ++
arch/x86/include/asm/xsave.h | 5 ++++-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 89270b4..1b00b01 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -216,6 +216,7 @@
#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
@@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32];
#define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2)
#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
+#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 0415cda..d3e3ea5 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -9,6 +9,8 @@
#define XSTATE_FP 0x1
#define XSTATE_SSE 0x2
#define XSTATE_YMM 0x4
+#define XSTATE_BNDREGS 0x8
+#define XSTATE_BNDCSR 0x10
#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
@@ -23,7 +25,8 @@
/*
* These are the features that the OS can handle currently.
*/
-#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
+#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | \
+ XSTATE_BNDREGS | XSTATE_BNDCSR)
#ifdef CONFIG_X86_64
#define REX_PREFIX "0x48, "
--
1.7.1
[-- Attachment #2: 0001-X86-Intel-MPX-definiation.patch --]
[-- Type: application/octet-stream, Size: 2254 bytes --]
From 3a1a011100b38a275d8c95468c12c483e316bb15 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Fri, 29 Nov 2013 01:27:00 +0800
Subject: [PATCH 1/4] X86: Intel MPX definiation
Signed-off-by: Xudong Hao <xudong.hao@intel.com>
Reviewed-by: Liu Jinsong <jinsong.liu@intel.com>
---
arch/x86/include/asm/cpufeature.h | 2 ++
arch/x86/include/asm/xsave.h | 5 ++++-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 89270b4..1b00b01 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -216,6 +216,7 @@
#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
@@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32];
#define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2)
#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
+#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 0415cda..d3e3ea5 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -9,6 +9,8 @@
#define XSTATE_FP 0x1
#define XSTATE_SSE 0x2
#define XSTATE_YMM 0x4
+#define XSTATE_BNDREGS 0x8
+#define XSTATE_BNDCSR 0x10
#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
@@ -23,7 +25,8 @@
/*
* These are the features that the OS can handle currently.
*/
-#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
+#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | \
+ XSTATE_BNDREGS | XSTATE_BNDCSR)
#ifdef CONFIG_X86_64
#define REX_PREFIX "0x48, "
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-12-06 8:22 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2013-12-02 16:43 [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation Liu, Jinsong
2013-12-02 17:39 ` Paolo Bonzini
2013-12-05 16:08 ` Paolo Bonzini
2013-12-05 22:59 ` H. Peter Anvin
2013-12-06 8:22 ` Paolo Bonzini
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2013-11-29 13:41 Liu, Jinsong
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