From: Richard Henderson <rth@twiddle.net>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
patches@linaro.org, Michael Matz <matz@suse.de>,
qemu-devel@nongnu.org,
Claudio Fontana <claudio.fontana@linaro.org>,
Dirk Mueller <dmueller@suse.de>,
Will Newton <will.newton@linaro.org>,
Laurent Desnogues <laurent.desnogues@gmail.com>,
kvmarm@lists.cs.columbia.edu,
Christoffer Dall <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 02/13] target-arm: A64: add support for logical (shifted register)
Date: Sat, 07 Dec 2013 05:49:14 +1300 [thread overview]
Message-ID: <52A2000A.3060704@twiddle.net> (raw)
In-Reply-To: <87d2la9v87.fsf@linaro.org>
On 12/06/2013 10:36 PM, Alex Bennée wrote:
>> While correct, surely better to work with tcg and select on opc:invert to
>> generate andc/orc/eqv?
>
> Shouldn't the TCG optimiser/back-end just be smart enough to figure it
> out? It seems clearer to express the tcg ops in terms of the front-end's
> meaning?
No, the TCG optimizer is really quite stupid. It only does constant folding
and dead code elimination. No peepholing or combination sorts of opts.
>> Also, isn't MOV (register) canonical for ORR (rn=31 && shift_amount=0), and MVN
>> (register) canonical for ORN (rn=31 && shift_amount=0), and both therefore also
>> worth a special case?
>
> I suspect I'm being overly cheeky to expect the optimiser to detect and
> optimise for that case as the ZR is a const ;-)
It would. But since register-register move is a rather common operation, it
will pay off to not require the optimizer to clean up that special case.
Thus I only recommend special casing the official aliases, not any operation
that could mathematically be considered an identity.
r~
next prev parent reply other threads:[~2013-12-06 16:49 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-05 21:51 [Qemu-devel] [PATCH 00/13] target-arm: A64 decoder set 2: misc logic and bit ops Peter Maydell
2013-12-05 21:51 ` [Qemu-devel] [PATCH 01/13] target-arm: A64: add support for conditional select Peter Maydell
2013-12-05 22:26 ` Richard Henderson
2013-12-05 22:31 ` Peter Maydell
2013-12-05 22:40 ` Richard Henderson
2013-12-06 12:45 ` Peter Maydell
2013-12-06 16:44 ` Richard Henderson
2013-12-06 17:23 ` Peter Maydell
2013-12-05 21:51 ` [Qemu-devel] [PATCH 02/13] target-arm: A64: add support for logical (shifted register) Peter Maydell
2013-12-05 22:39 ` Richard Henderson
2013-12-06 9:36 ` Alex Bennée
2013-12-06 16:49 ` Richard Henderson [this message]
2013-12-05 21:51 ` [Qemu-devel] [PATCH 03/13] target-arm: A64: add support for ADR and ADRP Peter Maydell
2013-12-05 22:41 ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 04/13] target-arm: A64: add support for EXTR Peter Maydell
2013-12-05 22:47 ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 05/13] target-arm: A64: add support for 2-src data processing and DIV Peter Maydell
2013-12-05 22:51 ` Richard Henderson
2013-12-05 23:09 ` Peter Maydell
2013-12-05 23:13 ` Richard Henderson
2013-12-05 23:21 ` C Fontana
2013-12-05 23:24 ` Eric Blake
2013-12-05 21:51 ` [Qemu-devel] [PATCH 06/13] target-arm: A64: add support for 2-src shift reg insns Peter Maydell
2013-12-05 22:52 ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 07/13] target-arm: A64: add support for 1-src data processing and CLZ Peter Maydell
2013-12-05 22:54 ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 08/13] target-arm: A64: add support for 1-src RBIT insn Peter Maydell
2013-12-05 22:56 ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 09/13] target-arm: A64: add support for 1-src REV insns Peter Maydell
2013-12-05 23:01 ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 10/13] target-arm: A64: add support for bitfield insns Peter Maydell
2013-12-05 23:05 ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits Peter Maydell
2013-12-05 23:06 ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 12/13] target-arm: A64: add support for 1-src CLS insn Peter Maydell
2013-12-05 23:06 ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 13/13] target-arm: A64: add support for logical (immediate) insns Peter Maydell
2013-12-05 23:39 ` Richard Henderson
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