From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:35389)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1Voyaq-0006Bn-25
	for qemu-devel@nongnu.org; Fri, 06 Dec 2013 11:49:40 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1Voyah-0007Q5-KV
	for qemu-devel@nongnu.org; Fri, 06 Dec 2013 11:49:31 -0500
Received: from mail-yh0-x229.google.com ([2607:f8b0:4002:c01::229]:34306)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1Voyah-0007Q1-HA
	for qemu-devel@nongnu.org; Fri, 06 Dec 2013 11:49:23 -0500
Received: by mail-yh0-f41.google.com with SMTP id f11so649013yha.14
	for <qemu-devel@nongnu.org>; Fri, 06 Dec 2013 08:49:23 -0800 (PST)
Sender: Richard Henderson <rth7680@gmail.com>
Message-ID: <52A2000A.3060704@twiddle.net>
Date: Sat, 07 Dec 2013 05:49:14 +1300
From: Richard Henderson <rth@twiddle.net>
MIME-Version: 1.0
References: <1386280289-27636-1-git-send-email-peter.maydell@linaro.org>
	<1386280289-27636-3-git-send-email-peter.maydell@linaro.org>
	<52A10093.3030708@twiddle.net> <87d2la9v87.fsf@linaro.org>
In-Reply-To: <87d2la9v87.fsf@linaro.org>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Subject: Re: [Qemu-devel] [PATCH 02/13] target-arm: A64: add support for
 logical (shifted register)
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>, patches@linaro.org, Michael Matz <matz@suse.de>, qemu-devel@nongnu.org, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 12/06/2013 10:36 PM, Alex Bennée wrote:
>> While correct, surely better to work with tcg and select on opc:invert to
>> generate andc/orc/eqv?
> 
> Shouldn't the TCG optimiser/back-end just be smart enough to figure it
> out? It seems clearer to express the tcg ops in terms of the front-end's
> meaning?

No, the TCG optimizer is really quite stupid.  It only does constant folding
and dead code elimination.  No peepholing or combination sorts of opts.

>> Also, isn't MOV (register) canonical for ORR (rn=31 && shift_amount=0), and MVN
>> (register) canonical for ORN (rn=31 && shift_amount=0), and both therefore also
>> worth a special case?
> 
> I suspect I'm being overly cheeky to expect the optimiser to detect and
> optimise for that case as the ZR is a const ;-)

It would.  But since register-register move is a rather common operation, it
will pay off to not require the optimizer to clean up that special case.

Thus I only recommend special casing the official aliases, not any operation
that could mathematically be considered an identity.


r~