From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38878) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Voynv-0000S6-Jm for qemu-devel@nongnu.org; Fri, 06 Dec 2013 12:03:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Voynn-0003AK-N2 for qemu-devel@nongnu.org; Fri, 06 Dec 2013 12:03:03 -0500 Received: from mail-yh0-x22b.google.com ([2607:f8b0:4002:c01::22b]:34135) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Voynn-0003AD-IQ for qemu-devel@nongnu.org; Fri, 06 Dec 2013 12:02:55 -0500 Received: by mail-yh0-f43.google.com with SMTP id a41so655329yho.2 for ; Fri, 06 Dec 2013 09:02:55 -0800 (PST) Sender: Richard Henderson Message-ID: <52A20336.9090002@twiddle.net> Date: Sat, 07 Dec 2013 06:02:46 +1300 From: Richard Henderson MIME-Version: 1.0 References: <1386335953-28876-1-git-send-email-peter.maydell@linaro.org> <1386335953-28876-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1386335953-28876-3-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 02/13] target-arm: A64: add support for logical (shifted register) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?ISO-8859-1?Q?Alex_Benn=E9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall On 12/07/2013 02:19 AM, Peter Maydell wrote: > From: Alexander Graf > > Add support for the instructions described in "C3.5.10 Logical > (shifted register)". > > We store the flags in the same locations as the 32 bit decoder. > This is slightly awkward when calculating 64 bit results, but seems > a better tradeoff than having to rework the whole 32 bit decoder > and also make 32 bit result calculation in A64 awkward. > > Signed-off-by: Alexander Graf > [claudio: some refactoring to avoid hidden allocation of temps, > rework flags, use enums for shift types, > renaming of functions] > Signed-off-by: Claudio Fontana > [PMM: Use TCG's andc/orc/eqv ops rather than manually inverting] > Signed-off-by: Peter Maydell > --- > target-arm/translate-a64.c | 197 ++++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 191 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson r~