From: Richard Henderson <rth@twiddle.net>
To: Aurelien Jarno <aurelien@aurel32.net>, qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [Qemu-devel] [PATCH v2 4/4] tcg/optimize: add known-zero bits compute for load ops
Date: Sat, 07 Dec 2013 06:53:36 +1300 [thread overview]
Message-ID: <52A20F20.8030503@twiddle.net> (raw)
In-Reply-To: <1378747670-25512-5-git-send-email-aurelien@aurel32.net>
On 09/10/2013 05:27 AM, Aurelien Jarno wrote:
> + CASE_OP_32_64(ld8u):
> + case INDEX_op_qemu_ld8u:
> + mask = 0xff;
> + break;
> + CASE_OP_32_64(ld16u):
> + case INDEX_op_qemu_ld16u:
> + mask = 0xffff;
> + break;
> + case INDEX_op_ld32u_i64:
> + case INDEX_op_qemu_ld32u:
> + mask = 0xffffffffu;
> + break;
> +
This could stand to be updated for the new INDEX_op_qemu_ld_{i32,i64} opcodes,
where you have to look at args[last] to find out the width and sign.
But this is still an improvement for the old opcodes.
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
next prev parent reply other threads:[~2013-12-06 17:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-09 17:27 [Qemu-devel] [PATCH v2 0/4] tcg/optimize: fixes and improvements Aurelien Jarno
2013-09-09 17:27 ` [Qemu-devel] [PATCH v2 1/4] tcg/optimize: fix known-zero bits for right shift ops Aurelien Jarno
2013-12-06 17:53 ` Richard Henderson
2014-02-16 5:42 ` Michael Roth
2013-09-09 17:27 ` [Qemu-devel] [PATCH v2 2/4] tcg/optimize: fix known-zero bits optimization Aurelien Jarno
2013-12-06 17:54 ` Richard Henderson
2013-09-09 17:27 ` [Qemu-devel] [PATCH v2 3/4] tcg/optimize: improve known-zero bits for 32-bit ops Aurelien Jarno
2013-12-06 17:54 ` Richard Henderson
2013-09-09 17:27 ` [Qemu-devel] [PATCH v2 4/4] tcg/optimize: add known-zero bits compute for load ops Aurelien Jarno
2013-12-06 17:53 ` Richard Henderson [this message]
2013-11-29 9:32 ` [Qemu-devel] [PATCH v2 0/4] tcg/optimize: fixes and improvements Paolo Bonzini
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