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Sender: Richard Henderson <rth7680@gmail.com>
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Date: Sat, 07 Dec 2013 06:53:36 +1300
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH v2 4/4] tcg/optimize: add known-zero bits
 compute for load ops
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To: Aurelien Jarno <aurelien@aurel32.net>, qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>

On 09/10/2013 05:27 AM, Aurelien Jarno wrote:
> +        CASE_OP_32_64(ld8u):
> +        case INDEX_op_qemu_ld8u:
> +            mask = 0xff;
> +            break;
> +        CASE_OP_32_64(ld16u):
> +        case INDEX_op_qemu_ld16u:
> +            mask = 0xffff;
> +            break;
> +        case INDEX_op_ld32u_i64:
> +        case INDEX_op_qemu_ld32u:
> +            mask = 0xffffffffu;
> +            break;
> +

This could stand to be updated for the new INDEX_op_qemu_ld_{i32,i64} opcodes,
where you have to look at args[last] to find out the width and sign.

But this is still an improvement for the old opcodes.

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~