From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53082) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VozbM-0004jg-S3 for qemu-devel@nongnu.org; Fri, 06 Dec 2013 12:54:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VozbI-0003Ti-Ds for qemu-devel@nongnu.org; Fri, 06 Dec 2013 12:54:08 -0500 Sender: Richard Henderson Message-ID: <52A20F35.5090002@twiddle.net> Date: Sat, 07 Dec 2013 06:53:57 +1300 From: Richard Henderson MIME-Version: 1.0 References: <1378747670-25512-1-git-send-email-aurelien@aurel32.net> <1378747670-25512-2-git-send-email-aurelien@aurel32.net> In-Reply-To: <1378747670-25512-2-git-send-email-aurelien@aurel32.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 1/4] tcg/optimize: fix known-zero bits for right shift ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , qemu-devel@nongnu.org Cc: Paolo Bonzini , qemu-stable@nongnu.org On 09/10/2013 05:27 AM, Aurelien Jarno wrote: > 32-bit versions of sar and shr ops should not propagate known-zero bits > from the unused 32 high bits. For sar it could even lead to wrong code > being generated. > > Cc: Richard Henderson > Cc: Paolo Bonzini > Cc: qemu-stable@nongnu.org > Signed-off-by: Aurelien Jarno > --- > tcg/optimize.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson r~