From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53377) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vozc9-0006Dv-Uq for qemu-devel@nongnu.org; Fri, 06 Dec 2013 12:55:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vozc5-0003dW-4p for qemu-devel@nongnu.org; Fri, 06 Dec 2013 12:54:57 -0500 Received: from mail-yh0-x22e.google.com ([2607:f8b0:4002:c01::22e]:44254) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vozc5-0003dS-1E for qemu-devel@nongnu.org; Fri, 06 Dec 2013 12:54:53 -0500 Received: by mail-yh0-f46.google.com with SMTP id l109so724253yhq.33 for ; Fri, 06 Dec 2013 09:54:52 -0800 (PST) Sender: Richard Henderson Message-ID: <52A20F67.9030603@twiddle.net> Date: Sat, 07 Dec 2013 06:54:47 +1300 From: Richard Henderson MIME-Version: 1.0 References: <1378747670-25512-1-git-send-email-aurelien@aurel32.net> <1378747670-25512-4-git-send-email-aurelien@aurel32.net> In-Reply-To: <1378747670-25512-4-git-send-email-aurelien@aurel32.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 3/4] tcg/optimize: improve known-zero bits for 32-bit ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , qemu-devel@nongnu.org Cc: Paolo Bonzini On 09/10/2013 05:27 AM, Aurelien Jarno wrote: > The shl_i32 op might set some bits of the unused 32 high bits of the > mask. Fix that by clearing the unused 32 high bits for all 32-bit ops > except load/store which operate on tl values. > > Cc: Richard Henderson > Cc: Paolo Bonzini > Signed-off-by: Aurelien Jarno > --- > tcg/optimize.c | 6 ++++++ > 1 file changed, 6 insertions(+) Reviewed-by: Richard Henderson r~