From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:55653)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1VqQeB-0002Fy-SU
	for qemu-devel@nongnu.org; Tue, 10 Dec 2013 11:59:08 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1VqQe3-0000Xp-D3
	for qemu-devel@nongnu.org; Tue, 10 Dec 2013 11:58:59 -0500
Received: from mail-vb0-x229.google.com ([2607:f8b0:400c:c02::229]:60794)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1VqQe3-0000Xi-8a
	for qemu-devel@nongnu.org; Tue, 10 Dec 2013 11:58:51 -0500
Received: by mail-vb0-f41.google.com with SMTP id m10so763484vbh.0
	for <qemu-devel@nongnu.org>; Tue, 10 Dec 2013 08:58:50 -0800 (PST)
Sender: Richard Henderson <rth7680@gmail.com>
Message-ID: <52A74844.7060902@twiddle.net>
Date: Tue, 10 Dec 2013 08:58:44 -0800
From: Richard Henderson <rth@twiddle.net>
MIME-Version: 1.0
References: <1386612744-1013-1-git-send-email-peter.maydell@linaro.org>
	<1386612744-1013-3-git-send-email-peter.maydell@linaro.org>
	<52A6271E.6050704@twiddle.net> <87wqjc6c3s.fsf@linaro.org>
In-Reply-To: <87wqjc6c3s.fsf@linaro.org>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Subject: Re: [Qemu-devel] [PATCH 2/9] target-arm: A64: add support for ldp
	(load pair)
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>, patches@linaro.org, Michael Matz <matz@suse.de>, qemu-devel@nongnu.org, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 12/10/2013 05:59 AM, Alex Bennée wrote:
>>> +    if (extend && is_signed) {
>>> +        g_assert(size < 3);
>>> +        tcg_gen_ext32u_i64(dest, dest);
>>> +    }
>>
>> Is it worth noticing in size==2 && !extend that is_signed can be forced false
>> to avoid the extra extension.
> 
> Sorry I don't quite follow, the extension only occurs if it's an explict
> extension into a 64 bit register. Or are you talking about avoiding
> using the extension logic in the generic tcg_gen_qemu_ld_i64 code?

It's not obvious from this patch, since its more about the later gpr loads.
I was thinking about size==4, signed, 32-bit.

I.e. size=10, opc=11.  But reading closer that's unallocated_encoding.  So the
answer for this patch is "no it's not worth it".

But looking forward through the other patches I see

> +        if (size == 3 && opc == 2) {
> +            /* PRFM - prefetch */
> +            return;
> +        }
> +        is_store = (opc == 0);
> +        is_signed = opc & (1<<1);
> +        is_extended = (size < 3) && (opc & 1);

whereas from the ARM I see

if opc<1> == '0' then
  // store or zero-extending load
else
  if size == '11' then
     memop = MemOp_PREFETCH;
     if opc<0> == '1' then UnallocatedEncoding();
  else
     // sign-extending load
     memop = MemOp_LOAD;
     if size == '10' && opc<0> == '1' then UnallocatedEncoding();

I.e. two undiagnosed unallocated_encoding.

BTW, I find (1<<1) harder to scan here than 2, but I wasn't going to mention
that while there was nothing else in the code to fix.


r~