From: Tom Musta <tommusta@gmail.com>
To: Richard Henderson <rth@twiddle.net>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions
Date: Tue, 10 Dec 2013 11:58:51 -0600 [thread overview]
Message-ID: <52A7565B.50704@gmail.com> (raw)
In-Reply-To: <52A65FAA.1070403@twiddle.net>
On 12/9/2013 6:26 PM, Richard Henderson wrote:
>> + tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \
>> + /* check for MIN div -1 */ \
>> + int l3 = gen_new_label(); \
>> + tcg_gen_brcondi_i64(TCG_COND_NE, rb, -1l, l3); \
>> + tcg_gen_brcondi_i64(TCG_COND_EQ, ra, INT64_MIN, lbl_ov); \
>
> The second test can never be true, since ra has 32 zero bits.
> Thus the first test is also pointless.
Hmm. Consider the case where GPR[RA] = 0xUUUUUUUU_80000000 (U=don't care) and
GPR[RB] = 0xUUUUUUUU_FFFFFFFF. Without these checks, I do not believe overflow
will be properly detected.
>
>> + gen_set_label(lbl_ov); /* overflow handling */ \
>> + \
>> + if (signed) { \
>> + tcg_gen_sari_i64(cpu_gpr[rD(ctx->opcode)], ra, 63); \
>> + } else { \
>> + tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], 0); \
>> + } \
>
> Divide by zero from the signed case reads an uninitialized ra here. While it's
> true that the result is undefined, I don't think we want to expose
> uninitialized reads to the TCG optimizer.
>
> Although... what is that sari for anyway? The result is undefined in the
> non-div-by-zero overflow case as well. We might as well use 0, or even
> 0xdeadbeef, all the time, no?
I don't disagree with the comment. I was being consistent with existing code for
divw/divd. I suspect whomever wrote this was trying to match the hardware's
implementation. But 0 is certainly a perfectly good undefined value and would
simplify the code.
next prev parent reply other threads:[~2013-12-10 17:59 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
2013-12-09 15:46 ` [Qemu-devel] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06 Tom Musta
2013-12-18 22:02 ` Scott Wood
2013-12-18 22:09 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2013-12-18 22:11 ` Scott Wood
2013-12-18 22:37 ` Alexander Graf
2013-12-19 15:35 ` Tom Musta
2013-12-19 17:17 ` Scott Wood
2013-12-09 15:46 ` [Qemu-devel] [PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction Tom Musta
2013-12-10 0:01 ` Richard Henderson
2013-12-10 17:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions Tom Musta
2013-12-10 0:05 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 04/18] target-ppc: Add ISA2.06 divde[o] Instructions Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions Tom Musta
2013-12-10 0:26 ` Richard Henderson
2013-12-10 17:58 ` Tom Musta [this message]
2013-12-10 18:30 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions Tom Musta
2013-12-10 0:31 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions Tom Musta
2013-12-10 0:41 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 08/18] target-ppc: Add ISA2.06 Float to Integer Instructions Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64 Tom Musta
2013-12-13 0:13 ` Peter Maydell
2013-12-16 15:20 ` Tom Musta
2013-12-16 15:24 ` Peter Maydell
2013-12-16 15:26 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 11/18] softfloat: Fix float64_to_uint32 Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 12/18] softfloat: Fix float64_to_uint32_round_to_zero Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 13/18] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 14/18] target-ppc: Fix and enable fri[mnpz] Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 15/18] target-ppc: Add ISA 2.06 ftdiv Instruction Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 16/18] target-ppc: Add ISA 2.06 ftsqrt Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 17/18] target-ppc: Enable frsqrtes on Power7 and Power8 Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 18/18] target-ppc: Add ISA2.06 lfiwzx Instruction Tom Musta
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