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Subject: Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address
	(0x80) on piix4_reset.
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To: Gal Hammer <gal@redhat.com>
Cc: Gal Hammer <ghammer@redhat.com>, qemu-stable@nongnu.org, qemu-devel@nongnu.org, "Michael S. Tsirkin" <mst@redhat.com>

Il 11/12/2013 12:04, Gal Hammer ha scritto:
> Michael,
> 
> True, I haven't figure it out yet, but the current status is that recover from sleep doesn't work.
> 
> As far as I can tell it could be either:
> 
> 1. piix4_reset shouldn't be call on resume.
> 2. memory_region_set_enabled (called in pm_io_space_update) shouldn't use config[0x80].
> 3. the config[0x80] shouldn't be zero in piix4_reset (current solution).
> 4. something else?
> 
> I'm not well familiar with the PIIX4 emulation and your help will be appreciated.

The datasheet says that config[0x80] is reset to 0.

The PIIX spec says that during S3 the chipset provides "Shadow registers
for standard AT write only registers to save and restore system state
information"  These are just for the 825x (DMA controller, PIC, PIT).
We do not emulate them and our BIOS does not support them.

I was told that a few memory controller registers survive S3, which in
our case would be the i440FX's PAM registers, but I don't think this
register should be one of them.

What guest is breaking and how?  Does the guest usually initialize this
register, or does the firmware (SeaBIOS) do that?  If the latter, this
could be a SeaBIOS bug instead.

Paolo