From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46178) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtI1p-000832-J4 for qemu-devel@nongnu.org; Wed, 18 Dec 2013 09:23:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VtI1g-0002Ok-VJ for qemu-devel@nongnu.org; Wed, 18 Dec 2013 09:23:13 -0500 Received: from mail-qc0-x22f.google.com ([2607:f8b0:400d:c01::22f]:58041) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtI1g-0002OT-Re for qemu-devel@nongnu.org; Wed, 18 Dec 2013 09:23:04 -0500 Received: by mail-qc0-f175.google.com with SMTP id e9so6147090qcy.20 for ; Wed, 18 Dec 2013 06:23:04 -0800 (PST) Sender: Paolo Bonzini Message-ID: <52B1AFC3.1050809@redhat.com> Date: Wed, 18 Dec 2013 15:22:59 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: <1386753670-11238-1-git-send-email-ghammer@redhat.com> In-Reply-To: <1386753670-11238-1-git-send-email-ghammer@redhat.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gal Hammer Cc: "seabios@seabios.org" , qemu-devel@nongnu.org, "Michael S. Tsirkin" Il 11/12/2013 10:21, Gal Hammer ha scritto: > Fix a bug that was introduced in commit c046e8c4. QEMU fails to > resume from suspend mode (S3). > > Signed-off-by: Gal Hammer > --- > hw/acpi/piix4.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > index 93849c8..5c736a4 100644 > --- a/hw/acpi/piix4.c > +++ b/hw/acpi/piix4.c > @@ -376,7 +376,6 @@ static void piix4_reset(void *opaque) > pci_conf[0x5b] = 0; > > pci_conf[0x40] = 0x01; /* PM io base read only bit */ > - pci_conf[0x80] = 0; > > if (s->kvm_enabled) { > /* Mark SMM as already inited (until KVM supports SMM). */ Note this is not the APIC base address, that one is 80h on the ISA bridge (function 0). You're changing the behavior for 80h on the power management function, which is function 3. The register is "PMBA—POWER MANAGEMENT BASE ADDRESS" and it is indeed initialized by SeaBIOS in piix4_pm_setup (src/fw/pciinit.c). Michael, perhaps a part of pci_setup (same file) should run on S3 resume? Paolo