From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56889) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtIot-0000Io-CO for qemu-devel@nongnu.org; Wed, 18 Dec 2013 10:14:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VtIon-0000Wx-DZ for qemu-devel@nongnu.org; Wed, 18 Dec 2013 10:13:55 -0500 Message-ID: <52B1BC4D.4020901@redhat.com> Date: Wed, 18 Dec 2013 17:16:29 +0200 From: Gal Hammer MIME-Version: 1.0 References: <1386753670-11238-1-git-send-email-ghammer@redhat.com> <52A83D1F.8060103@redhat.com> <20131211104437.GD9547@redhat.com> <42164188.5113689.1386759897161.JavaMail.root@redhat.com> <52B1AEDF.8050109@redhat.com> In-Reply-To: <52B1AEDF.8050109@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , Gal Hammer Cc: qemu-stable@nongnu.org, qemu-devel@nongnu.org, "Michael S. Tsirkin" On 18/12/2013 16:19, Paolo Bonzini wrote: > The PIIX spec says that during S3 the chipset provides "Shadow registers > for standard AT write only registers to save and restore system state > information" These are just for the 825x (DMA controller, PIC, PIT). > We do not emulate them and our BIOS does not support them. > > I was told that a few memory controller registers survive S3, which in > our case would be the i440FX's PAM registers, but I don't think this > register should be one of them. > > What guest is breaking and how? Does the guest usually initialize this > register, or does the firmware (SeaBIOS) do that? If the latter, this > could be a SeaBIOS bug instead. Both Windows and Linux guests are breaking when system is suspend. On system wakeup nothing occurs and the OS is not restored. I don't know the answer for the remaining questions. Thanks, Gal.