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From: Tom Musta <tommusta@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [V2 PATCH 11/18] softfloat: Fix float64_to_uint32
Date: Wed, 18 Dec 2013 12:23:16 -0600	[thread overview]
Message-ID: <52B1E814.3060102@gmail.com> (raw)
In-Reply-To: <CAFEAcA-yNxDH1zrH6=aeq-73x4ehe_7YbK5D_77Z-Bvqynb3jQ@mail.gmail.com>

On 12/18/2013 12:03 PM, Peter Maydell wrote:
> On 18 December 2013 17:32, Tom Musta <tommusta@gmail.com> wrote:
>> On 12/17/2013 11:45 AM, Peter Maydell wrote:
>>
>> This seems to assume that the only case where flags could be set in
>> float64_to_uint32 is the case where a large result is returned. Is
>> this really the case?
> 
> No, all it's assuming is that if we have the out-of-range
> case then the only flag that should be set is Invalid.
> In the "result is correct" case we return v and don't
> modify the flags from what float64_to_uint64() has set.
> 
> Do you think there are flags that should be allowed
> to be set by the conversion operation even if it is signaling
> Invalid because of out of range input? IEEE754-2008 section 7.1
> says "An invocation of [any operation except directly modifying
> the flags] might raise at most two status flags, overflow
> with inexact or underflow with inexact". That is, any operation
> might (1) raise no flags (2) raise just one flag (3) raise
> Overflow+Inexact (4) raise Underflow+Inexact.
> [QEMU/softfloat don't suport alternate exception handling
> so we can ignore the standard's verbiage about that.]
> 
> There is also the softfloat-specific float_flag_input_denormal,
> but I think that is also fine because it will only be set by the
> operation if we're squashing input denormals to zero, in
> which case the float-to-int conversion must always successfully
> return zero (because we squashed the input to plus or minus
> zero).
> 
> This is a bit complicated though, so maybe I missed a case?
> 
> thanks
> -- PMM
> 

I'm sorry Peter ... I misread your patch.  I see what you are doing
now.

I'll use your pattern, retest and resubmit.

  reply	other threads:[~2013-12-18 18:23 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-11 19:16 [Qemu-devel] [V2 PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06 Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction Tom Musta
2013-12-11 21:19   ` Richard Henderson
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 04/18] target-ppc: Add ISA2.06 divde[o] Instructions Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 08/18] target-ppc: Add ISA2.06 Float to Integer Instructions Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64 Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 11/18] softfloat: Fix float64_to_uint32 Tom Musta
2013-12-11 19:53   ` Peter Maydell
2013-12-11 20:39     ` Tom Musta
2013-12-17 17:45       ` Peter Maydell
2013-12-17 19:32         ` Peter Maydell
2013-12-18 17:32         ` Tom Musta
2013-12-18 18:03           ` Peter Maydell
2013-12-18 18:23             ` Tom Musta [this message]
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 12/18] softfloat: Fix float64_to_uint32_round_to_zero Tom Musta
2013-12-11 19:54   ` Peter Maydell
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 13/18] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 14/18] target-ppc: Fix and enable fri[mnpz] Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 15/18] target-ppc: Add ISA 2.06 ftdiv Instruction Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 16/18] target-ppc: Add ISA 2.06 ftsqrt Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 17/18] target-ppc: Enable frsqrtes on Power7 and Power8 Tom Musta
2013-12-11 19:16 ` [Qemu-devel] [V2 PATCH 18/18] target-ppc: Add ISA2.06 lfiwzx Instruction Tom Musta
2013-12-11 19:40 ` [Qemu-devel] [V2 PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Peter Maydell
2013-12-11 19:42   ` Tom Musta
2013-12-11 19:50     ` Peter Maydell

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