From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtkKH-0006DZ-6k for qemu-devel@nongnu.org; Thu, 19 Dec 2013 15:36:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VtkKC-00038L-FZ for qemu-devel@nongnu.org; Thu, 19 Dec 2013 15:36:09 -0500 Received: from mail-qe0-x22d.google.com ([2607:f8b0:400d:c02::22d]:56414) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtkKC-00038H-BI for qemu-devel@nongnu.org; Thu, 19 Dec 2013 15:36:04 -0500 Received: by mail-qe0-f45.google.com with SMTP id 6so1546517qea.18 for ; Thu, 19 Dec 2013 12:36:03 -0800 (PST) Sender: Richard Henderson Message-ID: <52B358AF.7090003@twiddle.net> Date: Thu, 19 Dec 2013 12:35:59 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1387293144-11554-1-git-send-email-peter.maydell@linaro.org> <1387293144-11554-15-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1387293144-11554-15-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 14/21] target-arm: A64: Implement minimal set of EL0-visible sysregs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?ISO-8859-1?Q?Alex_Benn=E9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall On 12/17/2013 07:12 AM, Peter Maydell wrote: > Implement an initial minimal set of EL0-visible system registers: > * NZCV > * FPCR > * FPSR > * CTR_EL0 > * DCZID_EL0 > > Signed-off-by: Peter Maydell > --- > target-arm/cpu.h | 3 ++- > target-arm/helper.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++ > target-arm/translate-a64.c | 54 +++++++++++++++++++++++++++++++++++++++++- > 3 files changed, 113 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~