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From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH 07/21] target-arm: A64: add support for 3
 src data proc insns
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Patch Tracking <patches@linaro.org>, Michael Matz <matz@suse.de>, QEMU Developers <qemu-devel@nongnu.org>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>, Christoffer Dall <christoffer.dall@linaro.org>

On 12/20/2013 05:18 AM, Peter Maydell wrote:
> On 19 December 2013 19:29, Richard Henderson <rth@twiddle.net> wrote:
>> On 12/17/2013 07:12 AM, Peter Maydell wrote:
>>> +    tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2);
>>> +    if (is_sub) {
>>> +        tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
>>> +    } else {
>>> +        tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
>>> +    }
>>
>> Perhaps worth noticing the RA=XZR special case for the MUL alias?
> 
> Yeah, makes sense: have adjusted to:
> +    if (ra == 31) {
> +        /* We special-case rA == XZR as it is the standard MUL alias */
> +        tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2);
> +    } else {

You need to handle (or dismiss) is_sub.

Either (ra == 31 && !is_sub) or

           if (is_sub) {
               tcg_gen_neg_i64(tcg_rd, tcg_rd);
           }

with tcg_rd pre-loaded along with tcg_op1 and tcg_op2.

That said, unlike MUL I don't expect MNEG to be common at all.

> +        tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2);
> +        if (is_sub) {
> +            tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
> +        } else {
> +            tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
> +        }
> +    }


r~