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Date: Fri, 20 Dec 2013 08:26:12 -0800
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH 02/21] target-arm: A64: add support for
 ld/st unsigned imm
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Patch Tracking <patches@linaro.org>, Michael Matz <matz@suse.de>, QEMU Developers <qemu-devel@nongnu.org>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>, Christoffer Dall <christoffer.dall@linaro.org>

On 12/20/2013 08:08 AM, Peter Maydell wrote:
>> In particular, opc = 2 && size = 2 should be unallocated.
> 
> This is LDRSW (immediate), not unallocated, isn't it?
> 
> I agree the decode logic isn't laid out the same as the ARM ARM,
> but I'm pretty sure it's correct.

Oops, typo: opc=3 && size=2.  Basically,


  if opc<1> == '0' then
    // store or zero-extending load
    memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE;
    regsize = if size == '11' then 64 else 32;
    signed = FALSE;
  else
    if size == '11' then
        memop = MemOp_PREFETCH;
        if opc<0> == '1' then UnallocatedEncoding();
    else
        // sign-extending load
        memop = MemOp_LOAD;
        if size == '10' && opc<0> == '1' then UnallocatedEncoding();

this one  ----^


r~