From: Laszlo Ersek <lersek@redhat.com>
To: Igor Mammedov <imammedo@redhat.com>
Cc: aliguori@amazon.com, "Michael S. Tsirkin" <mst@redhat.com>,
qemu-devel@nongnu.org, hutao@cn.fujitsu.com, jjherne@us.ibm.com,
brogers@suse.com, kraxel@redhat.com, stefanha@redhat.com,
kaneshige.kenji@jp.fujitsu.com, chen.fan.fnst@cn.fujitsu.com,
pbonzini@redhat.com
Subject: Re: [Qemu-devel] [PATCH 09/11] ACPI: move PRST OperationRegion into SSDT
Date: Mon, 23 Dec 2013 17:52:03 +0100 [thread overview]
Message-ID: <52B86A33.1090306@redhat.com> (raw)
In-Reply-To: <20131223172430.5107c3de@thinkpad>
On 12/23/13 17:24, Igor Mammedov wrote:
> On Mon, 23 Dec 2013 16:48:49 +0200
> "Michael S. Tsirkin" <mst@redhat.com> wrote:
>
>> On Mon, Dec 23, 2013 at 02:06:27PM +0100, Igor Mammedov wrote:
>>> On Mon, 23 Dec 2013 13:26:37 +0200
>>> "Michael S. Tsirkin" <mst@redhat.com> wrote:
>>>> Interesting. This seems to imply that it can't access
>>>> IO port for the disk. Which boot disk type are you using?
>>>> Is the _CRS resource overlapping any other resource
>>>> by any chance?
>>> Yes, I've dug in the issue more and it is indeed _CRS overlapping with PCI bus.
>>> PCI bus's IO ports are statically defined in acpi-dsdt-pci-crs.dsl and
>>> basically take all io ports except of 0xcf8-0xcff hole.
>>> Since PIIX4_PM and ICH9 LPC are PCI devices, it appears that PRST already
>>> covered by bus CRS, the same applies to PCI hotplug as well.
>>> So I was doing it wrong trying advertise bus resources out of bus scope.
>>
>> Yes, that's explicitly prohibited by the firmware specification.
>>
>>> What we need is to add PIIX4_PM/ICH9 LPC device definition with consumed IO
>>> ports CRS to PCI bus. Question is what PNP IDs they should use?
>>>
>>> It looks pretty much out of scope of cpu_hotplug and should be done for
>>> pci hotplug as well. So I'm ditching ACPI device and CRS parts from this
>>> series as not directly related.
>>> Adding PIIX4_PM/ICH9 LPC ACPI device could be done later and preferably
>>> for all resources consumed by it to make it right.
>>
>> Could be ok but are we using any new ports?
> yes, for q35. series adds 0xa18-0xa37 IO ports, it was requested by Gerd not
> to use 0xaf00-0xaf1f.
>
>> If yes then I think before doing that we should make sure _CRS for
>> the host bridge does not include them, or consume them
> I'm fine with making holes in PCI bus CRES template, I can do it for
> pci-hotplug as well while at it.
Can you guys please summarize the problem? (Just so I can understand.)
\_SB.PCI0 consumes 0x0CF8..0x0CFF, and is a resource producer for all
other IO ports (ie. it passes them on to child devices). Did we try to
consume such a passed-on port in a device that is *not* a child of
\_SB.PCI0?
And if so, what's the suggested solution? Make the new consumer a child
of \_SB.PCI0, or punch out the new (non-child) consumer's port range
from \_SB.PCI0's forwarding?
>> in some child device.
> that would be cleanest, but is there any suggestion what device(s) it would be
> for piix and ich9-lpc, i.e. which PNP IDs should we use?
You could browse
<http://www.plasma-online.de/english/identify/serial/pnp_id_pnp.html>.
One suggestion could be:
PNP0C02 -- General ID for reserving resources required by PnP
motherboard registers. (Not device specific.)
(AFAICS this PNP ID has been mentioned earlier in the thread.)
PNP0C08 -- ACPI system board hardware
(Also used already, apparently.)
Laszlo
next prev parent reply other threads:[~2013-12-23 16:52 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-13 16:22 [Qemu-devel] [PATCH 00/11] pc: CPU hotplug support for Q35 Igor Mammedov
2013-12-13 16:22 ` [Qemu-devel] [PATCH 01/11] acpi: piix4: remove not needed GPE0 mask Igor Mammedov
2013-12-19 14:16 ` Michael S. Tsirkin
2013-12-13 16:22 ` [Qemu-devel] [PATCH 02/11] acpi: factor out common pm_update_sci() into acpi core Igor Mammedov
2013-12-19 14:16 ` Michael S. Tsirkin
2013-12-13 16:22 ` [Qemu-devel] [PATCH 03/11] acpi: factor out common cpu hotplug code for PIIX4/Q35 Igor Mammedov
2013-12-19 14:14 ` Michael S. Tsirkin
2013-12-19 15:13 ` Igor Mammedov
2013-12-13 16:22 ` [Qemu-devel] [PATCH 04/11] acpi/piix4: add readonly "cpu-hotplug-io-base" property Igor Mammedov
2013-12-13 16:22 ` [Qemu-devel] [PATCH 05/11] acpi: ich9: allow guest to clear SCI rised by GPE Igor Mammedov
2013-12-19 14:16 ` Michael S. Tsirkin
2013-12-13 16:22 ` [Qemu-devel] [PATCH 06/11] acpi/ich9: add CPU hotplug handling to Q35 machine Igor Mammedov
2013-12-19 14:18 ` Michael S. Tsirkin
2013-12-19 15:17 ` Igor Mammedov
2013-12-19 15:33 ` Michael S. Tsirkin
2013-12-13 16:22 ` [Qemu-devel] [PATCH 07/11] ACPI: Q35 DSDT: fix CPU hotplug GPE0.2 handler Igor Mammedov
2013-12-13 16:22 ` [Qemu-devel] [PATCH 08/11] ACPI/DSDT-CPU: cleanup bogus comment Igor Mammedov
2013-12-13 16:22 ` [Qemu-devel] [PATCH 09/11] ACPI: move PRST OperationRegion into SSDT Igor Mammedov
2013-12-16 19:30 ` Michael S. Tsirkin
2013-12-16 20:38 ` Igor Mammedov
2013-12-16 21:13 ` Laszlo Ersek
2013-12-16 21:22 ` Laszlo Ersek
2013-12-16 21:53 ` Igor Mammedov
2013-12-17 10:39 ` Michael S. Tsirkin
2013-12-16 21:44 ` Laszlo Ersek
2013-12-16 21:59 ` Igor Mammedov
2013-12-16 22:22 ` Laszlo Ersek
2013-12-16 23:13 ` Igor Mammedov
2013-12-16 19:53 ` Michael S. Tsirkin
2013-12-16 22:15 ` Igor Mammedov
2013-12-22 14:51 ` Igor Mammedov
2013-12-23 11:26 ` Michael S. Tsirkin
2013-12-23 13:06 ` Igor Mammedov
2013-12-23 14:48 ` Michael S. Tsirkin
2013-12-23 16:24 ` Igor Mammedov
2013-12-23 16:52 ` Laszlo Ersek [this message]
2013-12-28 0:39 ` Igor Mammedov
2013-12-23 16:55 ` Michael S. Tsirkin
2013-12-13 16:22 ` [Qemu-devel] [PATCH 10/11] ACPI: set CPU hotplug io base dynamically Igor Mammedov
2013-12-13 16:22 ` [Qemu-devel] [PATCH 11/11] ACPI: update ssdt-misc.hex.generated acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated Igor Mammedov
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