From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43709) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvC23-0006Qp-0p for qemu-devel@nongnu.org; Mon, 23 Dec 2013 15:23:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VvC1y-0003sm-9h for qemu-devel@nongnu.org; Mon, 23 Dec 2013 15:23:18 -0500 Received: from mail-pb0-x229.google.com ([2607:f8b0:400e:c01::229]:50954) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvC1y-0003sg-1V for qemu-devel@nongnu.org; Mon, 23 Dec 2013 15:23:14 -0500 Received: by mail-pb0-f41.google.com with SMTP id jt11so5652919pbb.14 for ; Mon, 23 Dec 2013 12:23:13 -0800 (PST) Sender: Richard Henderson Message-ID: <52B89BAD.3030307@twiddle.net> Date: Mon, 23 Dec 2013 12:23:09 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1387752607-23755-1-git-send-email-peter.maydell@linaro.org> <1387752607-23755-17-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1387752607-23755-17-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 16/25] target-arm: Widen thread-local register state fields to 64 bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?ISO-8859-1?Q?Alex_Benn=E9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall On 12/22/2013 02:49 PM, Peter Maydell wrote: > The common pattern for system registers in a 64-bit capable ARM > CPU is that when in AArch32 the cp15 register is a view of the > bottom 32 bits of the 64-bit AArch64 system register; writes in > AArch32 leave the top half unchanged. The most natural way to > model this is to have the state field in the CPU struct be a > 64 bit value, and simply have the AArch32 TCG code operate on > a pointer to its lower half. > > For aarch64-linux-user the only registers we need to share like > this are the thread-local-storage ones. Widen their fields to > 64 bits and provide the 64 bit reginfo struct to make them > visible in AArch64 state. Note that minor cleanup of the AArch64 > system register encoding space means We can share the TPIDR_EL1 > reginfo but need split encodings for TPIDR_EL0 and TPIDRRO_EL0. > > Since we're touching almost every line in QEMU that uses the > c13_tls* fields in this patch anyway, we take the opportunity > to rename them in line with the standard ARM architectural names > for these registers. > > Signed-off-by: Peter Maydell > --- > linux-user/aarch64/target_cpu.h | 5 ++++- > linux-user/arm/target_cpu.h | 2 +- > linux-user/main.c | 2 +- > target-arm/cpu.h | 18 +++++++++++++++--- > target-arm/helper.c | 22 +++++++++++++++------- > 5 files changed, 36 insertions(+), 13 deletions(-) Reviewed-by: Richard Henderson r~