Re: [Qemu-devel] [PATCH v2 21/25] target-arm: A64: support for ld/st/cl exclusive

[Richard Henderson <rth@twiddle.net>]

On 12/22/2013 02:50 PM, Peter Maydell wrote:
> From: Michael Matz <matz@suse.de>
> 
> This implement exclusive loads/stores for aarch64 along the lines of
> arm32 and ppc implementations. The exclusive load remembers the address
> and loaded value. The exclusive store throws an an exception which uses
> those values to check for equality in a proper exclusive region.
> 
> This is not actually the architecture mandated semantics (for either
> AArch32 or AArch64) but it is close enough for typical guest code
> sequences to work correctly, and saves us from having to monitor all
> guest stores. It's fairly easy to come up with test cases where we
> don't behave like hardware - we don't for example model cache line
> behaviour. However in the common patterns this works, and the existing
> 32 bit ARM exclusive access implementation has the same limitations.
> 
> AArch64 also implements new acquire/release loads/stores (which may be
> either exclusive or non-exclusive). These imposes extra ordering
> constraints on memory operations (ie they act as if they have an implicit
> barrier built into them). As TCG is single-threaded all our barriers
> are no-ops, so these just behave like normal loads and stores.
> 
> Signed-off-by: Michael Matz <matz@suse.de>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  linux-user/main.c          | 127 +++++++++++++++++++++++++++++++++++-
>  target-arm/translate-a64.c | 156 ++++++++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 277 insertions(+), 6 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~