From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56521) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvD8v-0007H2-3a for qemu-devel@nongnu.org; Mon, 23 Dec 2013 16:34:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VvD8q-0006jd-Q9 for qemu-devel@nongnu.org; Mon, 23 Dec 2013 16:34:29 -0500 Received: from mail-pd0-x22b.google.com ([2607:f8b0:400e:c02::22b]:40635) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvD8q-0006jU-Ix for qemu-devel@nongnu.org; Mon, 23 Dec 2013 16:34:24 -0500 Received: by mail-pd0-f171.google.com with SMTP id z10so5571407pdj.2 for ; Mon, 23 Dec 2013 13:34:23 -0800 (PST) Sender: Richard Henderson Message-ID: <52B8AC5B.1030005@twiddle.net> Date: Mon, 23 Dec 2013 13:34:19 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1387752607-23755-1-git-send-email-peter.maydell@linaro.org> <1387752607-23755-22-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1387752607-23755-22-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v2 21/25] target-arm: A64: support for ld/st/cl exclusive List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?B?QWxleCBCZW5uw6ll?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall On 12/22/2013 02:50 PM, Peter Maydell wrote: > From: Michael Matz > > This implement exclusive loads/stores for aarch64 along the lines of > arm32 and ppc implementations. The exclusive load remembers the address > and loaded value. The exclusive store throws an an exception which uses > those values to check for equality in a proper exclusive region. > > This is not actually the architecture mandated semantics (for either > AArch32 or AArch64) but it is close enough for typical guest code > sequences to work correctly, and saves us from having to monitor all > guest stores. It's fairly easy to come up with test cases where we > don't behave like hardware - we don't for example model cache line > behaviour. However in the common patterns this works, and the existing > 32 bit ARM exclusive access implementation has the same limitations. > > AArch64 also implements new acquire/release loads/stores (which may be > either exclusive or non-exclusive). These imposes extra ordering > constraints on memory operations (ie they act as if they have an implicit > barrier built into them). As TCG is single-threaded all our barriers > are no-ops, so these just behave like normal loads and stores. > > Signed-off-by: Michael Matz > Signed-off-by: Alex Bennée > Signed-off-by: Peter Maydell > --- > linux-user/main.c | 127 +++++++++++++++++++++++++++++++++++- > target-arm/translate-a64.c | 156 ++++++++++++++++++++++++++++++++++++++++++++- > 2 files changed, 277 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson r~