From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56196) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvTsY-0005mz-9P for qemu-devel@nongnu.org; Tue, 24 Dec 2013 10:26:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VvTsP-0007u6-Sa for qemu-devel@nongnu.org; Tue, 24 Dec 2013 10:26:42 -0500 Sender: Richard Henderson Message-ID: <52B9A7A5.9090201@twiddle.net> Date: Tue, 24 Dec 2013 07:26:29 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1387399747-4994-1-git-send-email-tommusta@gmail.com> <1387399747-4994-6-git-send-email-tommusta@gmail.com> In-Reply-To: <1387399747-4994-6-git-send-email-tommusta@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [V3 PATCH 05/14] target-ppc: Add ISA 2.06 divwe[u][o] Instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org On 12/18/2013 12:48 PM, Tom Musta wrote: > + tcg_gen_div_i64(cpu_gpr[rD(ctx->opcode)], ra, rb); \ > + tmp0 = tcg_temp_local_new(); \ > + /* does the result fit in 32 bits? */ \ > + tcg_gen_ext32s_i64(tmp0, cpu_gpr[rD(ctx->opcode)]); \ > + tcg_gen_brcond_i64(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], tmp0, \ > + lbl_ov); \ > + tcg_temp_free(tmp0); \ tmp0 does not need to be a local temp, as it's not used across basic blocks. I do wonder if this wouldn't be better as a helper, what with all of the branches. TCG essentially won't optimize any of this. r~