From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56652) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvTuR-0007B3-81 for qemu-devel@nongnu.org; Tue, 24 Dec 2013 10:28:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VvTuK-0000Gp-5c for qemu-devel@nongnu.org; Tue, 24 Dec 2013 10:28:39 -0500 Sender: Richard Henderson Message-ID: <52B9A81B.7080205@twiddle.net> Date: Tue, 24 Dec 2013 07:28:27 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1387399747-4994-1-git-send-email-tommusta@gmail.com> <1387399747-4994-7-git-send-email-tommusta@gmail.com> In-Reply-To: <1387399747-4994-7-git-send-email-tommusta@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [V3 PATCH 06/14] target-ppc: Add ISA2.06 lbarx, lharx Instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org On 12/18/2013 12:48 PM, Tom Musta wrote: > This patch adds the byte and halfword variations of the Load and > Reserve instructions. Since there is much commonality among > all forms of Load and Reserve, a common macro is provided and the > existing implementations of lwarx and ldarx are re-implemented using > this macro. > > V2: Fixed bug in aligment check for lharx (caught by Richard). > > Signed-off-by: Tom Musta > --- > target-ppc/translate.c | 50 +++++++++++++++++++++++------------------------ > 1 files changed, 24 insertions(+), 26 deletions(-) Reviewed-by: Richard Henderson r~