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Subject: Re: [Qemu-devel] [PATCH 02/10] target-arm: A64: Fix vector register
 access on bigendian hosts
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Patch Tracking <patches@linaro.org>, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, QEMU Developers <qemu-devel@nongnu.org>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>, Christoffer Dall <christoffer.dall@linaro.org>

On 12/30/2013 07:28 AM, Peter Maydell wrote:
> Yeah, we could do that. Will the optimiser optimise away the unnecessary
> extra load of the unused high 32 bits for the "32 bit or smaller" case on
> a 32 bit host CPU?

It should.

We do transform qemu_st_i64 to qemu_st_i32 as appropriate for 32-bit hosts,
making the high part of the tcg ld_i64 dead.


r~