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Date: Fri, 10 Jan 2014 10:05:11 -0800
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add SIMD ld/st
	multiple
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Laurent Desnogues <laurent.desnogues@gmail.com>, patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +    TCGMemOp memop =  MO_TE + size;

Double space after =.  Multiple occurrences.

> +    if (is_postidx) {
> +        int rm = extract32(insn, 16, 5);
> +        if (rm == 31) {
> +            tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
> +        } else {
> +            tcg_gen_add_i64(cpu_reg_sp(s, rn), cpu_reg(s, rn), cpu_reg(s, rm));
> +        }

Second cpu_reg must be cpu_reg_sp as well.  Maybe better to hoist load of
tcg_rn to before initial assignment of tcg_addr?


r~