From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Patch Tracking" <patches@linaro.org>,
"Michael Matz" <matz@suse.de>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Alexander Graf" <agraf@suse.de>,
"Claudio Fontana" <claudio.fontana@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>,
"Christoffer Dall" <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add SIMD ld/st multiple
Date: Fri, 10 Jan 2014 10:28:41 -0800 [thread overview]
Message-ID: <52D03BD9.10908@twiddle.net> (raw)
In-Reply-To: <CAFEAcA-9okjN8syonAsj1ooC0UKYR3fr-KXtCyNdPGDFJMju3w@mail.gmail.com>
On 01/10/2014 10:18 AM, Peter Maydell wrote:
>> > Maybe better to hoist load of
>> > tcg_rn to before initial assignment of tcg_addr?
> Not sure what you have in mind here. Pulling the
> cpu_reg_sp() call out one level like:
>
> if (is_postidx) {
> int rm = extract32(insn, 16, 5);
> TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
> if (rm == 31) {
> tcg_gen_mov_i64(tcg_rn, tcg_addr);
> } else {
> tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
> }
> }
>
> seems like a good idea though.
I was thinking
TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
TCGv_i64 tcg_addr = tcg_temp_new_i64();
tcg_gen_mov_i64(tcg_addr, tcg_rn);
up above. But even as you have there is good.
r~
next prev parent reply other threads:[~2014-01-10 18:29 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-10 17:12 [Qemu-devel] [PATCH 00/10] A64 SIMD patchset one: ld/st, C3.6.1..C3.6.7 Peter Maydell
2014-01-10 17:12 ` [Qemu-devel] [PATCH 01/10] target-arm: A64: Add SIMD ld/st multiple Peter Maydell
2014-01-10 18:05 ` Richard Henderson
2014-01-10 18:18 ` Peter Maydell
2014-01-10 18:28 ` Richard Henderson [this message]
2014-01-10 18:37 ` Peter Maydell
2014-01-10 19:00 ` Richard Henderson
2014-01-10 17:12 ` [Qemu-devel] [PATCH 02/10] target-arm: A64: Add SIMD ld/st single Peter Maydell
2014-01-10 18:12 ` Richard Henderson
2014-01-10 17:12 ` [Qemu-devel] [PATCH 03/10] target-arm: A64: Add decode skeleton for SIMD data processing insns Peter Maydell
2014-01-10 18:55 ` Richard Henderson
2014-01-10 19:05 ` Richard Henderson
2014-01-11 0:01 ` Peter Maydell
2014-01-10 17:12 ` [Qemu-devel] [PATCH 04/10] target-arm: A64: Add SIMD EXT Peter Maydell
2014-01-10 19:13 ` Richard Henderson
2014-01-10 17:12 ` [Qemu-devel] [PATCH 05/10] target-arm: A64: Add SIMD TBL/TBLX Peter Maydell
2014-01-10 19:19 ` Richard Henderson
2014-01-10 17:12 ` [Qemu-devel] [PATCH 06/10] target-arm: A64: Add SIMD ZIP/UZP/TRN Peter Maydell
2014-01-10 19:29 ` Richard Henderson
2014-01-11 8:30 ` Alex Bennée
2014-01-10 17:12 ` [Qemu-devel] [PATCH 07/10] target-arm: A64: Add SIMD across-lanes instructions Peter Maydell
2014-01-10 19:38 ` Richard Henderson
2014-01-10 17:12 ` [Qemu-devel] [PATCH 08/10] target-arm: A64: Add SIMD copy operations Peter Maydell
2014-01-10 19:50 ` Richard Henderson
2014-01-10 17:12 ` [Qemu-devel] [PATCH 09/10] target-arm: A64: Add SIMD modified immediate group Peter Maydell
2014-01-10 20:00 ` Richard Henderson
2014-01-10 17:12 ` [Qemu-devel] [PATCH 10/10] target-arm: A64: Add SIMD scalar copy instructions Peter Maydell
2014-01-10 20:03 ` Richard Henderson
2014-01-15 15:10 ` Claudio Fontana
2014-01-15 18:01 ` Peter Maydell
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