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Subject: Re: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add SIMD ld/st
	multiple
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Laurent Desnogues <laurent.desnogues@gmail.com>, Patch Tracking <patches@linaro.org>, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, QEMU Developers <qemu-devel@nongnu.org>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>, Christoffer Dall <christoffer.dall@linaro.org>

On 01/10/2014 10:37 AM, Peter Maydell wrote:
> On 10 January 2014 18:28, Richard Henderson <rth@twiddle.net> wrote:
>> On 01/10/2014 10:18 AM, Peter Maydell wrote:
>>>>> Maybe better to hoist load of
>>>>> tcg_rn to before initial assignment of tcg_addr?
>>> Not sure what you have in mind here. Pulling the
>>> cpu_reg_sp() call out one level like:
>>>
>>>     if (is_postidx) {
>>>         int rm = extract32(insn, 16, 5);
>>>         TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
>>>         if (rm == 31) {
>>>             tcg_gen_mov_i64(tcg_rn, tcg_addr);
>>>         } else {
>>>             tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
>>>         }
>>>     }
>>>
>>> seems like a good idea though.
>>
>> I was thinking
>>
>>   TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
>>   TCGv_i64 tcg_addr = tcg_temp_new_i64();
>>   tcg_gen_mov_i64(tcg_addr, tcg_rn);
>>
>> up above.  But even as you have there is good.
> 
> Oh, right. Yes, I like that -- have made the change.

Don't forget the free, of course.  Or use new_tmp_a64.


r~