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Sender: Richard Henderson <rth7680@gmail.com>
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Date: Fri, 10 Jan 2014 11:29:14 -0800
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH 06/10] target-arm: A64: Add SIMD ZIP/UZP/TRN
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Laurent Desnogues <laurent.desnogues@gmail.com>, patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, =?ISO-8859-1?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +    for (i = 0; i < elements; i++) {
> +        switch (opcode) {
> +        case 1: /* UZP1/2 */
> +        {
> +            int midpoint = elements / 2;
> +            if (i < midpoint) {
> +                read_vec_element(s, tcg_res, rn, 2 * i + part, size);
> +            } else {
> +                read_vec_element(s, tcg_res, rm,
> +                                 2 * (i - midpoint) + part, size);
> +            }
> +            break;
> +        }

You're generating up to 16 * 3 + 2 = 50 opcodes here.  I do wonder if it
wouldn't be better to implement these as helpers.  But,

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~