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Sender: Richard Henderson <rth7680@gmail.com>
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Date: Mon, 13 Jan 2014 08:07:51 -0800
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH v2 01/10] target-arm: A64: Add SIMD ld/st
	multiple
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 01/13/2014 06:13 AM, Peter Maydell wrote:
> From: Alex Bennée <alex.bennee@linaro.org>
> 
> This adds support support for the SIMD load/store
> multiple category of instructions.
> 
> This also brings in a couple of helper functions for manipulating
> sections of the SIMD registers:
> 
>   * do_vec_get - fetch value from a slice of a vector register
>   * do_vec_set - set a slice of a vector register
> 
> which use vec_reg_offset for consistent processing of offsets in an
> endian aware manner. There are also additional helpers:
> 
>   * do_vec_ld - load value into SIMD
>   * do_vec_st - store value from SIMD
> 
> which load or store a slice of a vector register to memory.
> These don't zero extend like the fp variants.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> public v1->v2 changes:
>  removed stray double-spacing
>  fixed incorrect handling of rn==sp, cleaned up tcg_rn code
> ---
>  target-arm/translate-a64.c | 250 ++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 248 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~