From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51413) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W3S6y-0003JJ-Nb for qemu-devel@nongnu.org; Wed, 15 Jan 2014 10:10:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W3S6s-0001gc-SP for qemu-devel@nongnu.org; Wed, 15 Jan 2014 10:10:32 -0500 Received: from lhrrgout.huawei.com ([194.213.3.17]:27886) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W3S6s-0001g0-KL for qemu-devel@nongnu.org; Wed, 15 Jan 2014 10:10:26 -0500 Message-ID: <52D6A4CB.20503@huawei.com> Date: Wed, 15 Jan 2014 16:10:03 +0100 From: Claudio Fontana MIME-Version: 1.0 References: <1389373972-27686-1-git-send-email-peter.maydell@linaro.org> <1389373972-27686-11-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1389373972-27686-11-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 10/10] target-arm: A64: Add SIMD scalar copy instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: Laurent Desnogues , Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , =?ISO-8859-1?Q?Alex_Benn=E9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Hello Peter, a missing return here I think: On 10.01.2014 18:12, Peter Maydell wrote: > Add support for the SIMD scalar copy instruction group (C3.6.7), > which consists of the single instruction DUP (element, scalar). > > Signed-off-by: Peter Maydell > --- > target-arm/translate-a64.c | 42 +++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 41 insertions(+), 1 deletion(-) > > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index 153a28a..70a8314 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -5084,6 +5084,35 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, > tcg_temp_free_i64(tmp); > } > > +/* C6.3.31 DUP (element, scalar) > + * 31 21 20 16 15 10 9 5 4 0 > + * +-----------------------+--------+-------------+------+------+ > + * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | > + * +-----------------------+--------+-------------+------+------+ > + */ > +static void handle_simd_dupes(DisasContext *s, int rd, int rn, > + int imm5) > +{ > + int size = ctz32(imm5); > + int index; > + TCGv_i64 tmp; > + > + if (size > 3) { > + unallocated_encoding(s); > + return; > + } > + > + index = imm5 >> (size + 1); > + > + /* This instruction just extracts the specified element and > + * zero-extends it into the bottom of the destination register. > + */ > + tmp = tcg_temp_new_i64(); > + read_vec_element(s, tmp, rn, index, size); > + write_fp_dreg(s, rd, tmp); > + tcg_temp_free_i64(tmp); > +} > + > /* C6.3.32 DUP (General) > * > * 31 30 29 21 20 16 15 10 9 5 4 0 > @@ -5412,7 +5441,18 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) > */ > static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) > { > - unsupported_encoding(s, insn); > + int rd = extract32(insn, 0, 5); > + int rn = extract32(insn, 5, 5); > + int imm4 = extract32(insn, 11, 4); > + int imm5 = extract32(insn, 16, 5); > + int op = extract32(insn, 29, 1); > + > + if (op != 0 || imm4 != 0) { > + unallocated_encoding(s); add a return here. > + } > + > + /* DUP (element, scalar) */ > + handle_simd_dupes(s, rd, rn, imm5); > } > > /* C3.6.8 AdvSIMD scalar pairwise > Ciao, Claudio -- Claudio Fontana Server Virtualization Architect Huawei Technologies Duesseldorf GmbH Riesstraße 25 - 80992 München office: +49 89 158834 4135 mobile: +49 15253060158