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Subject: Re: [Qemu-devel] [PATCH 5/8] target-arm: A64: Add logic ops from
	SIMD 3 same group
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 01/17/2014 10:44 AM, Peter Maydell wrote:
> +            /* AND, BIC, ORR, ORN */
> +            if (extract32(size, 0, 1)) {
> +                tcg_gen_not_i64(tcg_op2, tcg_op2);
> +            }
> +            if (extract32(size, 1, 1)) {
> +                tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2);
> +            } else {
> +                tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2);
> +            }

It would be worthwhile to generate andc and orc directly instead
of a separate not.


r~