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Subject: Re: [Qemu-devel] [PATCH 6/8] target-arm: A64: Add integer ops from
 SIMD 3-same group
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?ISO-8859-1?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 01/17/2014 10:44 AM, Peter Maydell wrote:
> +            switch (opcode) {
> +            case 0x6: /* CMGT, CMHI */
> +            {
> +                NeonGenFn *ceqtstfns[3][2] = {
...
> +            case 0x7: /* CMGE, CMHS */
> +            {
> +                NeonGenFn *ceqtstfns[3][2] = {
...
> +            case 0x11: /* CMTST, CMEQ */
> +            {
> +                NeonGenFn *ceqtstfns[3][2] = {

Oh, and cut and paste on those names?  Perhaps it would be less confusing to
just name them all "fns" and let the specific code block imply the rest?


r~