From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48308) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W5j6e-0005eY-NX for qemu-devel@nongnu.org; Tue, 21 Jan 2014 16:43:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W5j6V-00041m-1M for qemu-devel@nongnu.org; Tue, 21 Jan 2014 16:43:36 -0500 Received: from mail-pb0-x22c.google.com ([2607:f8b0:400e:c01::22c]:61715) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W5j6U-00041i-OX for qemu-devel@nongnu.org; Tue, 21 Jan 2014 16:43:26 -0500 Received: by mail-pb0-f44.google.com with SMTP id rq2so8951537pbb.31 for ; Tue, 21 Jan 2014 13:43:25 -0800 (PST) Sender: Richard Henderson Message-ID: <52DEE9F6.4050501@twiddle.net> Date: Tue, 21 Jan 2014 13:43:18 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1389984257-6822-1-git-send-email-peter.maydell@linaro.org> <1389984257-6822-9-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1389984257-6822-9-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 8/8] target-arm: A64: Add SIMD shift by immediate List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?B?QWxleCBCZW5uw6ll?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall On 01/17/2014 10:44 AM, Peter Maydell wrote: > +/* Common SHL/SLI - Shift left with an optional insert */ > +static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src, > + bool insert, int shift) > +{ > + tcg_gen_shli_i64(tcg_src, tcg_src, shift); > + if (insert) { > + /* SLI */ > + uint64_t mask = (1ULL << shift) - 1; > + tcg_gen_andi_i64(tcg_res, tcg_res, mask); > + tcg_gen_or_i64(tcg_res, tcg_res, tcg_src); This is tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, shift, 64 - shift); We do already special case such remaining-width deposits for hosts that don't implement deposit, so we should get the exact same insn sequence for x86. > + tcg_gen_mov_i64(tcg_res, tcg_src); Which means for the else you can elide the move and just shift directly into the result. r~