* [Qemu-devel] Intel AVX instructions
@ 2014-01-22 16:27 Xin Tong
2014-01-22 17:35 ` Paolo Bonzini
0 siblings, 1 reply; 6+ messages in thread
From: Xin Tong @ 2014-01-22 16:27 UTC (permalink / raw)
To: QEMU Developers
Intel AVX instructions have been out for some time since sandy-bridge.
Is there value to support it in QEMU. I am thinking abut a google
summer of code this year to bring support for AVX/AVX2.0 to QEMU.
Xin
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] Intel AVX instructions
2014-01-22 16:27 [Qemu-devel] Intel AVX instructions Xin Tong
@ 2014-01-22 17:35 ` Paolo Bonzini
2014-01-22 19:35 ` Xin Tong
0 siblings, 1 reply; 6+ messages in thread
From: Paolo Bonzini @ 2014-01-22 17:35 UTC (permalink / raw)
To: Xin Tong, QEMU Developers, Stefan Hajnoczi
Il 22/01/2014 17:27, Xin Tong ha scritto:
> Intel AVX instructions have been out for some time since sandy-bridge.
> Is there value to support it in QEMU. I am thinking abut a google
> summer of code this year to bring support for AVX/AVX2.0 to QEMU.
Yes, that can be a nice project indeed! Of course you are welcome to
contribute to QEMU even before we submit our GSoC application. For
example, it's possible to add XSAVE/XRSTOR support even without AVX
support, even though there is no real processors with this combination.
Paolo
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] Intel AVX instructions
2014-01-22 17:35 ` Paolo Bonzini
@ 2014-01-22 19:35 ` Xin Tong
2014-01-22 20:06 ` Peter Maydell
2014-01-22 20:19 ` Richard Henderson
0 siblings, 2 replies; 6+ messages in thread
From: Xin Tong @ 2014-01-22 19:35 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: QEMU Developers, Stefan Hajnoczi
It seems that BOCHS have AVX instructions support in interpreter. I am
thinking an easy/reliable way to do this would be generate helper
calls to emulate every AVX instruction and follow how BOCHS emulates
them. Then depending on the expected frequency and difficulties, one
can decide whether to move some of the instructions into TCG JITted
code ?
Also, it would be desirable to use the MMX/SSE structures and
functions that already exist in QEMU target-i386/translate.c
please comment.
Xin
On Wed, Jan 22, 2014 at 11:35 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> Il 22/01/2014 17:27, Xin Tong ha scritto:
>
>> Intel AVX instructions have been out for some time since sandy-bridge.
>> Is there value to support it in QEMU. I am thinking abut a google
>> summer of code this year to bring support for AVX/AVX2.0 to QEMU.
>
>
> Yes, that can be a nice project indeed! Of course you are welcome to
> contribute to QEMU even before we submit our GSoC application. For example,
> it's possible to add XSAVE/XRSTOR support even without AVX support, even
> though there is no real processors with this combination.
>
> Paolo
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] Intel AVX instructions
2014-01-22 19:35 ` Xin Tong
@ 2014-01-22 20:06 ` Peter Maydell
2014-01-22 20:19 ` Richard Henderson
1 sibling, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2014-01-22 20:06 UTC (permalink / raw)
To: Xin Tong; +Cc: Paolo Bonzini, QEMU Developers, Stefan Hajnoczi
On 22 January 2014 19:35, Xin Tong <trent.tong@gmail.com> wrote:
> It seems that BOCHS have AVX instructions support in interpreter. I am
> thinking an easy/reliable way to do this would be generate helper
> calls to emulate every AVX instruction and follow how BOCHS emulates
> them. Then depending on the expected frequency and difficulties, one
> can decide whether to move some of the instructions into TCG JITted
> code ?
I would recommend implementing them from scratch for QEMU
based on the Intel architecture documentation. That will produce
much nicer results.
> Also, it would be desirable to use the MMX/SSE structures and
> functions that already exist in QEMU target-i386/translate.c
It would certainly be advisable to use them where there is
commonality.
thanks
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] Intel AVX instructions
2014-01-22 19:35 ` Xin Tong
2014-01-22 20:06 ` Peter Maydell
@ 2014-01-22 20:19 ` Richard Henderson
2014-01-22 21:57 ` Xin Tong
1 sibling, 1 reply; 6+ messages in thread
From: Richard Henderson @ 2014-01-22 20:19 UTC (permalink / raw)
To: Xin Tong, Paolo Bonzini; +Cc: QEMU Developers, Stefan Hajnoczi
On 01/22/2014 11:35 AM, Xin Tong wrote:
> It seems that BOCHS have AVX instructions support in interpreter. I am
> thinking an easy/reliable way to do this would be generate helper
> calls to emulate every AVX instruction and follow how BOCHS emulates
> them. Then depending on the expected frequency and difficulties, one
> can decide whether to move some of the instructions into TCG JITted
> code ?
>
> Also, it would be desirable to use the MMX/SSE structures and
> functions that already exist in QEMU target-i386/translate.c
The way you should start is by re-using the existing SSE helpers.
There are several things one must consider with AVX:
(1) Old SSE insns. These do not modify bits 128 and higher.
(2) SSE insns encoded with VEX. These zero bits 128 and higher.
(3) AVX insns. These (generally) modify all 256 bits.
Case 1 can be handled by doing nothing with the existing helpers.
Case 2 can be handled by using the existing helper, followed by a couple of
stores to zero the high part.
Case 3 can, with only a few exceptions, be handled by using the existing helper
twice on the two halves. Thankfully the existing helpers work with host
pointers rather than register numbers.
That will cover at least 90% of the AVX2 instruction set.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] Intel AVX instructions
2014-01-22 20:19 ` Richard Henderson
@ 2014-01-22 21:57 ` Xin Tong
0 siblings, 0 replies; 6+ messages in thread
From: Xin Tong @ 2014-01-22 21:57 UTC (permalink / raw)
To: Richard Henderson; +Cc: Paolo Bonzini, QEMU Developers, Stefan Hajnoczi
Richard:
That is very intelligient way to support AVX. I believe Bochs uses
similar technique.
On Wed, Jan 22, 2014 at 2:19 PM, Richard Henderson <rth@twiddle.net> wrote:
> On 01/22/2014 11:35 AM, Xin Tong wrote:
>> It seems that BOCHS have AVX instructions support in interpreter. I am
>> thinking an easy/reliable way to do this would be generate helper
>> calls to emulate every AVX instruction and follow how BOCHS emulates
>> them. Then depending on the expected frequency and difficulties, one
>> can decide whether to move some of the instructions into TCG JITted
>> code ?
>>
>> Also, it would be desirable to use the MMX/SSE structures and
>> functions that already exist in QEMU target-i386/translate.c
>
> The way you should start is by re-using the existing SSE helpers.
>
> There are several things one must consider with AVX:
>
> (1) Old SSE insns. These do not modify bits 128 and higher.
> (2) SSE insns encoded with VEX. These zero bits 128 and higher.
> (3) AVX insns. These (generally) modify all 256 bits.
>
> Case 1 can be handled by doing nothing with the existing helpers.
>
> Case 2 can be handled by using the existing helper, followed by a couple of
> stores to zero the high part.
>
> Case 3 can, with only a few exceptions, be handled by using the existing helper
> twice on the two halves. Thankfully the existing helpers work with host
> pointers rather than register numbers.
>
> That will cover at least 90% of the AVX2 instruction set.
>
>
> r~
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-01-22 21:57 UTC | newest]
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2014-01-22 16:27 [Qemu-devel] Intel AVX instructions Xin Tong
2014-01-22 17:35 ` Paolo Bonzini
2014-01-22 19:35 ` Xin Tong
2014-01-22 20:06 ` Peter Maydell
2014-01-22 20:19 ` Richard Henderson
2014-01-22 21:57 ` Xin Tong
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