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Date: Thu, 23 Jan 2014 08:55:31 -0800
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH v2 7/8] target-arm: A64: Add simple SIMD
 3-same floating point ops
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?ISO-8859-1?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 01/23/2014 07:28 AM, Peter Maydell wrote:
> +            /* Single */
> +            TCGv_i32 tcg_op1 = tcg_temp_new_i32();
> +            TCGv_i32 tcg_op2 = tcg_temp_new_i32();
> +            TCGv_i32 tcg_res = tcg_temp_new_i32();
> +            TCGv_i64 tcg_tmp = tcg_temp_new_i64();
> +
> +            read_vec_element(s, tcg_tmp, rn, pass, MO_32);
> +            tcg_gen_trunc_i64_i32(tcg_op1, tcg_tmp);
> +            read_vec_element(s, tcg_tmp, rm, pass, MO_32);
> +            tcg_gen_trunc_i64_i32(tcg_op2, tcg_tmp);

Update for new _i32 helpers.


r~