From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41978) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W6Toy-0004HQ-Ay for qemu-devel@nongnu.org; Thu, 23 Jan 2014 18:36:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W6Toq-0000hV-Tw for qemu-devel@nongnu.org; Thu, 23 Jan 2014 18:36:28 -0500 Received: from cantor2.suse.de ([195.135.220.15]:52378 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W6Toq-0000hG-OP for qemu-devel@nongnu.org; Thu, 23 Jan 2014 18:36:20 -0500 Message-ID: <52E1A76F.1080802@suse.de> Date: Fri, 24 Jan 2014 00:36:15 +0100 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] QEMU ARM946 emulation, DIGIC, and MPU fault handling List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , QEMU Developers Cc: Antony Pavlov Am 23.01.2014 23:25, schrieb Peter Maydell: > This bug would also affect the ARMv7M CPU (Cortex-M3) we emulate, > except that as far as I can tell we don't implement its MPU interface a= t all! > (it uses memory mapped registers rather than cp15 regs, and they just > aren't wired up in armv7m_nvic.c...) That matches my memories of investigating Cortex-R4. There is some MPU code present somewhere, but it appeared to be for some older CPU, possibly OMAP2. Regards, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg