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Date: Tue, 28 Jan 2014 09:13:35 -0800
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH 10/21] target-arm: A64: Implement remaining
 non-pairwise int SIMD 3-reg-same insns
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com>, patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?ISO-8859-1?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 01/26/2014 11:25 AM, Peter Maydell wrote:
> @@ -6773,9 +6801,9 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
>              case 0x8: /* SSHL, USHL */
>              {
>                  static NeonGenTwoOpFn * const fns[3][2] = {
> -                    { gen_helper_neon_shl_u8, gen_helper_neon_shl_s8 },
> -                    { gen_helper_neon_shl_u16, gen_helper_neon_shl_s16 },
> -                    { gen_helper_neon_shl_u32, gen_helper_neon_shl_s32 },
> +                    { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 },
> +                    { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 },
> +                    { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 },
>                  };
>                  genfn = fns[size][u];
>                  break;

Oops, I clearly missed this in the review of the previous patch.
But these bug fixes ought to be folded into the previous.

Otherwise,

Reviewed-by: Richard Henderson <rth@twiddle.net>

> +            case 0xd: /* SMIN, UMIN */
> +            {
> +                static NeonGenTwoOpFn * const fns[3][2] = {
> +                    { gen_helper_neon_min_s8, gen_helper_neon_min_u8 },
> +                    { gen_helper_neon_min_s16, gen_helper_neon_min_u16 },
> +                    { gen_helper_neon_min_s32, gen_helper_neon_min_u32 },
> +                };
> +                genfn = fns[size][u];
> +                break;

Out of curiosity, what logic are you applying to using the neon helper
functions and implementing stuff inline?

It appears that you're implementing all of the 64-bit stuff inline, but using
the existing 32-bit helpers, even if the helpers are remarkably small, like
some of these.


r~