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Sender: Richard Henderson <rth7680@gmail.com>
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Date: Tue, 28 Jan 2014 09:21:39 -0800
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise
 integer ops from 3-reg-same SIMD
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com>, patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?ISO-8859-1?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 01/26/2014 11:25 AM, Peter Maydell wrote:
> +/* Helper functions for pairwise 32 bit comparisons */
> +static void gen_pmax_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
> +{
> +    tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2);
> +}
> +
> +static void gen_pmax_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
> +{
> +    tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2);
> +}
> +
> +static void gen_pmin_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
> +{
> +    tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2);
> +}
> +
> +static void gen_pmin_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
> +{
> +    tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2);
> +}

These are exactly the sort of helpers I expected to see in the previous patch.
Thus my question re neon_{min,max}_{s,u}32.

Otherwise,

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~