Re: [Qemu-devel] [PATCH 20/21] target-arm: A64: Add 2-reg-misc REV* instructions

[Richard Henderson <rth@twiddle.net>]

On 01/26/2014 11:25 AM, Peter Maydell wrote:
> +    int elements = dsize / esize;
> +    int i;
> +    TCGv_i64 tcg_rd_hi, tcg_rd, tcg_rn;
> +
> +    if (opsz >= 3) {
> +        unallocated_encoding(s);
> +        return;
> +    }
> +
> +    tcg_rn = tcg_temp_new_i64();
> +    tcg_rd = tcg_const_i64(0);
> +    tcg_rd_hi = tcg_const_i64(0);
> +
> +    for (i = 0; i < elements; i++) {
> +        int e_rev = (i & 0xf) ^ revmask;
> +        int off = e_rev * esize;
> +        read_vec_element(s, tcg_rn, rn, i, size);
> +        if (off >= 64) {
> +            tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi, tcg_rn, off - 64, esize);
> +        } else {
> +            tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);
> +        }
> +    }
> +    write_vec_element(s, tcg_rd, rd, 0, MO_64);
> +    write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);

Surely a special case for esize == 8 is in order, since that's bswap.

Otherwise,

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~