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Date: Mon, 03 Feb 2014 13:21:31 -0800
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH v2 02/13] target-arm: A64: Implement
 remaining non-pairwise int SIMD 3-reg-same insns
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com>, patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?ISO-8859-1?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 02/01/2014 02:59 PM, Peter Maydell wrote:
> Implement the SIMD 3-reg-same instructions where the size == 3 case
> is reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX,
> UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL,
> SQRDMULH, SQDMULH. (None of these have scalar-3-same versions.)
> This completes the non-pairwise integer instructions in this category.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~