* [Qemu-devel] [PATCH v2 0/4] mips32r5 with UFR
@ 2014-01-24 16:18 Petar Jovanovic
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5 Petar Jovanovic
` (3 more replies)
0 siblings, 4 replies; 19+ messages in thread
From: Petar Jovanovic @ 2014-01-24 16:18 UTC (permalink / raw)
To: qemu-devel; +Cc: petar.jovanovic, aurelien, Petar Jovanovic
Version 2 of the patch series to add mips32r5-generic model with UFR feature.
It includes extra patch to add support for Config4.
Petar Jovanovic (4):
target-mips: add CPU definition for MIPS32R5
target-mips: add support for CP0_Config4
target-mips: add support for CP0_Config5
target-mips: add user-mode FR switch support for MIPS32r5
target-mips/cpu.h | 13 +++++++++++
target-mips/helper.h | 4 +++-
target-mips/mips-defs.h | 8 +++++++
target-mips/op_helper.c | 53 +++++++++++++++++++++++++++++++++++++++---
target-mips/translate.c | 39 +++++++++++++++++++++++++++----
target-mips/translate_init.c | 43 ++++++++++++++++++++++++++++++++++
6 files changed, 152 insertions(+), 8 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-01-24 16:18 [Qemu-devel] [PATCH v2 0/4] mips32r5 with UFR Petar Jovanovic
@ 2014-01-24 16:18 ` Petar Jovanovic
2014-02-03 23:55 ` Petar Jovanovic
` (2 more replies)
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 2/4] target-mips: add support for CP0_Config4 Petar Jovanovic
` (2 subsequent siblings)
3 siblings, 3 replies; 19+ messages in thread
From: Petar Jovanovic @ 2014-01-24 16:18 UTC (permalink / raw)
To: qemu-devel; +Cc: petar.jovanovic, aurelien
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/mips-defs.h | 8 ++++++++
target-mips/translate_init.c | 25 +++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#define ISA_MIPS32R2 0x00000040
#define ISA_MIPS64 0x00000080
#define ISA_MIPS64R2 0x00000100
+#define ISA_MIPS32R3 0x00000200
+#define ISA_MIPS32R5 0x00000400
/* MIPS ASEs. */
#define ASE_MIPS16 0x00001000
@@ -64,6 +66,12 @@
#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
+/* MIPS Technologies "Release 3" */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies "Release 5" */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ /* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+ .name = "mips32r5-generic",
+ .CP0_PRid = 0x00019700,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#if defined(TARGET_MIPS64)
{
.name = "R4000",
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v2 2/4] target-mips: add support for CP0_Config4
2014-01-24 16:18 [Qemu-devel] [PATCH v2 0/4] mips32r5 with UFR Petar Jovanovic
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5 Petar Jovanovic
@ 2014-01-24 16:18 ` Petar Jovanovic
2014-02-08 3:35 ` Eric Johnson
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 3/4] target-mips: add support for CP0_Config5 Petar Jovanovic
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 4/4] target-mips: add user-mode FR switch support for MIPS32r5 Petar Jovanovic
3 siblings, 1 reply; 19+ messages in thread
From: Petar Jovanovic @ 2014-01-24 16:18 UTC (permalink / raw)
To: qemu-devel; +Cc: petar.jovanovic, aurelien
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Add CP0_Config4, define rw_bitmask.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/cpu.h | 3 +++
target-mips/helper.h | 1 +
target-mips/op_helper.c | 6 ++++++
target-mips/translate.c | 15 +++++++++++++--
target-mips/translate_init.c | 9 ++++++++-
5 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 9caf447..e8216ab 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -368,6 +368,9 @@ struct CPUMIPSState {
#define CP0C3_MT 2
#define CP0C3_SM 1
#define CP0C3_TL 0
+ uint32_t CP0_Config4;
+ uint32_t CP0_Config4_rw_bitmask;
+#define CP0C4_M 31
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 1a8b86d..9e4508b 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -134,6 +134,7 @@ DEF_HELPER_2(mtc0_ebase, void, env, tl)
DEF_HELPER_2(mttc0_ebase, void, env, tl)
DEF_HELPER_2(mtc0_config0, void, env, tl)
DEF_HELPER_2(mtc0_config2, void, env, tl)
+DEF_HELPER_2(mtc0_config4, void, env, tl)
DEF_HELPER_2(mtc0_lladdr, void, env, tl)
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 8e3a6d7..ed8dde8 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1489,6 +1489,12 @@ void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
}
+void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
+{
+ env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
+ (arg1 & env->CP0_Config4_rw_bitmask);
+}
+
void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
{
target_long mask = env->CP0_LLAddr_rw_bitmask;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index ef0a2c3..db2f430 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4405,7 +4405,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
rn = "Config3";
break;
- /* 4,5 are reserved */
+ case 4:
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
+ rn = "Config4";
+ break;
+ /* 5 is reserved */
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
@@ -4982,7 +4986,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* ignored, read only */
rn = "Config3";
break;
- /* 4,5 are reserved */
+ case 4:
+ gen_helper_mtc0_config4(cpu_env, arg);
+ rn = "Config4";
+ ctx->bstate = BS_STOP;
+ break;
+ /* 5 is reserved */
/* 6,7 are implementation dependent */
case 6:
/* ignored */
@@ -15916,6 +15925,8 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Config1 = env->cpu_model->CP0_Config1;
env->CP0_Config2 = env->cpu_model->CP0_Config2;
env->CP0_Config3 = env->cpu_model->CP0_Config3;
+ env->CP0_Config4 = env->cpu_model->CP0_Config4;
+ env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
env->CP0_Config6 = env->cpu_model->CP0_Config6;
env->CP0_Config7 = env->cpu_model->CP0_Config7;
env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index d74a0af..a0398cd 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -45,6 +45,9 @@
(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
(0 << CP0C3_SM) | (0 << CP0C3_TL))
+#define MIPS_CONFIG4 \
+((0 << CP0C4_M))
+
/* MMU types, the first four entries have the same layout as the
CP0C0_MT field. */
enum mips_mmu_types {
@@ -64,6 +67,8 @@ struct mips_def_t {
int32_t CP0_Config1;
int32_t CP0_Config2;
int32_t CP0_Config3;
+ int32_t CP0_Config4;
+ int32_t CP0_Config4_rw_bitmask;
int32_t CP0_Config6;
int32_t CP0_Config7;
target_ulong CP0_LLAddr_rw_bitmask;
@@ -345,7 +350,9 @@ static const mips_def_t mips_defs[] =
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),
+ .CP0_Config4 = MIPS_CONFIG4,
+ .CP0_Config4_rw_bitmask = 0,
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v2 3/4] target-mips: add support for CP0_Config5
2014-01-24 16:18 [Qemu-devel] [PATCH v2 0/4] mips32r5 with UFR Petar Jovanovic
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5 Petar Jovanovic
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 2/4] target-mips: add support for CP0_Config4 Petar Jovanovic
@ 2014-01-24 16:18 ` Petar Jovanovic
2014-02-08 3:35 ` Eric Johnson
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 4/4] target-mips: add user-mode FR switch support for MIPS32r5 Petar Jovanovic
3 siblings, 1 reply; 19+ messages in thread
From: Petar Jovanovic @ 2014-01-24 16:18 UTC (permalink / raw)
To: qemu-devel; +Cc: petar.jovanovic, aurelien
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/cpu.h | 10 ++++++++++
target-mips/helper.h | 1 +
target-mips/op_helper.c | 6 ++++++
target-mips/translate.c | 14 ++++++++++++--
target-mips/translate_init.c | 12 +++++++++++-
5 files changed, 40 insertions(+), 3 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index e8216ab..60c8061 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -73,6 +73,7 @@ struct CPUMIPSFPUContext {
float_status fp_status;
/* fpu implementation/revision register (fir) */
uint32_t fcr0;
+#define FCR0_UFRP 28
#define FCR0_F64 22
#define FCR0_L 21
#define FCR0_W 20
@@ -371,6 +372,15 @@ struct CPUMIPSState {
uint32_t CP0_Config4;
uint32_t CP0_Config4_rw_bitmask;
#define CP0C4_M 31
+ uint32_t CP0_Config5;
+ uint32_t CP0_Config5_rw_bitmask;
+#define CP0C5_M 31
+#define CP0C5_K 30
+#define CP0C5_CV 29
+#define CP0C5_EVA 28
+#define CP0C5_MSAEn 27
+#define CP0C5_UFR 2
+#define CP0C5_NFExists 0
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 9e4508b..b82f8e8 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -135,6 +135,7 @@ DEF_HELPER_2(mttc0_ebase, void, env, tl)
DEF_HELPER_2(mtc0_config0, void, env, tl)
DEF_HELPER_2(mtc0_config2, void, env, tl)
DEF_HELPER_2(mtc0_config4, void, env, tl)
+DEF_HELPER_2(mtc0_config5, void, env, tl)
DEF_HELPER_2(mtc0_lladdr, void, env, tl)
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index ed8dde8..eaf4d26 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1495,6 +1495,12 @@ void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
(arg1 & env->CP0_Config4_rw_bitmask);
}
+void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
+{
+ env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
+ (arg1 & env->CP0_Config5_rw_bitmask);
+}
+
void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
{
target_long mask = env->CP0_LLAddr_rw_bitmask;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index db2f430..02a90cb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4409,7 +4409,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
rn = "Config4";
break;
- /* 5 is reserved */
+ case 5:
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
+ rn = "Config5";
+ break;
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
@@ -4991,7 +4994,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "Config4";
ctx->bstate = BS_STOP;
break;
- /* 5 is reserved */
+ case 5:
+ gen_helper_mtc0_config5(cpu_env, arg);
+ rn = "Config5";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
+ break;
/* 6,7 are implementation dependent */
case 6:
/* ignored */
@@ -15927,6 +15935,8 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Config3 = env->cpu_model->CP0_Config3;
env->CP0_Config4 = env->cpu_model->CP0_Config4;
env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
+ env->CP0_Config5 = env->cpu_model->CP0_Config5;
+ env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
env->CP0_Config6 = env->cpu_model->CP0_Config6;
env->CP0_Config7 = env->cpu_model->CP0_Config7;
env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index a0398cd..3d4dc88 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -48,6 +48,9 @@
#define MIPS_CONFIG4 \
((0 << CP0C4_M))
+#define MIPS_CONFIG5 \
+((0 << CP0C5_M))
+
/* MMU types, the first four entries have the same layout as the
CP0C0_MT field. */
enum mips_mmu_types {
@@ -69,6 +72,8 @@ struct mips_def_t {
int32_t CP0_Config3;
int32_t CP0_Config4;
int32_t CP0_Config4_rw_bitmask;
+ int32_t CP0_Config5;
+ int32_t CP0_Config5_rw_bitmask;
int32_t CP0_Config6;
int32_t CP0_Config7;
target_ulong CP0_LLAddr_rw_bitmask;
@@ -351,8 +356,13 @@ static const mips_def_t mips_defs[] =
(1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),
- .CP0_Config4 = MIPS_CONFIG4,
+ .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
.CP0_Config4_rw_bitmask = 0,
+ .CP0_Config5 = MIPS_CONFIG5,
+ .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
+ (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
+ (1 << CP0C5_MSAEn) | (0 << CP0C5_UFR) |
+ (0 << CP0C5_NFExists),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v2 4/4] target-mips: add user-mode FR switch support for MIPS32r5
2014-01-24 16:18 [Qemu-devel] [PATCH v2 0/4] mips32r5 with UFR Petar Jovanovic
` (2 preceding siblings ...)
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 3/4] target-mips: add support for CP0_Config5 Petar Jovanovic
@ 2014-01-24 16:18 ` Petar Jovanovic
2014-02-08 3:35 ` Eric Johnson
3 siblings, 1 reply; 19+ messages in thread
From: Petar Jovanovic @ 2014-01-24 16:18 UTC (permalink / raw)
To: qemu-devel; +Cc: petar.jovanovic, aurelien
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR.
helper_ctc1 has been extended with an additional parameter rt to check
requirements for UFR feature.
Definition of mips32r5-generic has been modified to include support for UFR.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/helper.h | 2 +-
target-mips/op_helper.c | 41 ++++++++++++++++++++++++++++++++++++++---
target-mips/translate.c | 14 ++++++++++++--
target-mips/translate_init.c | 9 +++++----
4 files changed, 56 insertions(+), 10 deletions(-)
diff --git a/target-mips/helper.h b/target-mips/helper.h
index b82f8e8..8c7921a 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -179,7 +179,7 @@ DEF_HELPER_2(yield, tl, env, tl)
/* CP1 functions */
DEF_HELPER_2(cfc1, tl, env, i32)
-DEF_HELPER_3(ctc1, void, env, tl, i32)
+DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
DEF_HELPER_2(float_cvtd_s, i64, env, i32)
DEF_HELPER_2(float_cvtd_w, i64, env, i32)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index eaf4d26..2ef6633 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2199,12 +2199,23 @@ static inline void restore_flush_mode(CPUMIPSState *env)
target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
{
- target_ulong arg1;
+ target_ulong arg1 = 0;
switch (reg) {
case 0:
arg1 = (int32_t)env->active_fpu.fcr0;
break;
+ case 1:
+ /* UFR Support - Read Status FR */
+ if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
+ if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
+ arg1 = (int32_t)
+ ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
+ } else {
+ helper_raise_exception(env, EXCP_RI);
+ }
+ }
+ break;
case 25:
arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
break;
@@ -2222,9 +2233,33 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
return arg1;
}
-void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
+void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
{
- switch(reg) {
+ switch (fs) {
+ case 1:
+ /* UFR Alias - Reset Status FR */
+ if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
+ return;
+ }
+ if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
+ env->CP0_Status &= ~(1 << CP0St_FR);
+ compute_hflags(env);
+ } else {
+ helper_raise_exception(env, EXCP_RI);
+ }
+ break;
+ case 4:
+ /* UNFR Alias - Set Status FR */
+ if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
+ return;
+ }
+ if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
+ env->CP0_Status |= (1 << CP0St_FR);
+ compute_hflags(env);
+ } else {
+ helper_raise_exception(env, EXCP_RI);
+ }
+ break;
case 25:
if (arg1 & 0xffffff00)
return;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 02a90cb..083f6ab 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -6818,7 +6818,12 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
break;
case 3:
/* XXX: For now we support only a single FPU context. */
- gen_helper_0e1i(ctc1, t0, rd);
+ {
+ TCGv_i32 fs_tmp = tcg_const_i32(rd);
+
+ gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
+ tcg_temp_free_i32(fs_tmp);
+ }
break;
/* COP2: Not implemented. */
case 4:
@@ -7254,7 +7259,12 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
break;
case OPC_CTC1:
gen_load_gpr(t0, rt);
- gen_helper_0e1i(ctc1, t0, fs);
+ {
+ TCGv_i32 fs_tmp = tcg_const_i32(fs);
+
+ gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
+ tcg_temp_free_i32(fs_tmp);
+ }
opn = "ctc1";
break;
#if defined(TARGET_MIPS64)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 3d4dc88..29d39e2 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -358,18 +358,19 @@ static const mips_def_t mips_defs[] =
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),
.CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
.CP0_Config4_rw_bitmask = 0,
- .CP0_Config5 = MIPS_CONFIG5,
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
.CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
(1 << CP0C5_CV) | (0 << CP0C5_EVA) |
- (1 << CP0C5_MSAEn) | (0 << CP0C5_UFR) |
+ (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
(0 << CP0C5_NFExists),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x3778FF1F,
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
- (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
+ (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x93 << FCR0_PRID),
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5 Petar Jovanovic
@ 2014-02-03 23:55 ` Petar Jovanovic
2014-02-04 13:59 ` Petar Jovanovic
2014-02-08 3:34 ` Eric Johnson
2014-02-10 13:51 ` Andreas Färber
2 siblings, 1 reply; 19+ messages in thread
From: Petar Jovanovic @ 2014-02-03 23:55 UTC (permalink / raw)
To: Petar Jovanovic, qemu-devel@nongnu.org; +Cc: aurelien@aurel32.net
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
Regards,
Petar
________________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Friday, January 24, 2014 5:18 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurelien@aurel32.net
Subject: [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/mips-defs.h | 8 ++++++++
target-mips/translate_init.c | 25 +++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#define ISA_MIPS32R2 0x00000040
#define ISA_MIPS64 0x00000080
#define ISA_MIPS64R2 0x00000100
+#define ISA_MIPS32R3 0x00000200
+#define ISA_MIPS32R5 0x00000400
/* MIPS ASEs. */
#define ASE_MIPS16 0x00001000
@@ -64,6 +66,12 @@
#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
+/* MIPS Technologies "Release 3" */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies "Release 5" */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ /* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+ .name = "mips32r5-generic",
+ .CP0_PRid = 0x00019700,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#if defined(TARGET_MIPS64)
{
.name = "R4000",
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-02-03 23:55 ` Petar Jovanovic
@ 2014-02-04 13:59 ` Petar Jovanovic
2014-02-10 11:21 ` Petar Jovanovic
0 siblings, 1 reply; 19+ messages in thread
From: Petar Jovanovic @ 2014-02-04 13:59 UTC (permalink / raw)
To: Petar Jovanovic, qemu-devel@nongnu.org; +Cc: aurelien@aurel32.net
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
Regards,
Petar
________________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Friday, January 24, 2014 5:18 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurelien@aurel32.net
Subject: [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/mips-defs.h | 8 ++++++++
target-mips/translate_init.c | 25 +++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#define ISA_MIPS32R2 0x00000040
#define ISA_MIPS64 0x00000080
#define ISA_MIPS64R2 0x00000100
+#define ISA_MIPS32R3 0x00000200
+#define ISA_MIPS32R5 0x00000400
/* MIPS ASEs. */
#define ASE_MIPS16 0x00001000
@@ -64,6 +66,12 @@
#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
+/* MIPS Technologies "Release 3" */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies "Release 5" */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ /* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+ .name = "mips32r5-generic",
+ .CP0_PRid = 0x00019700,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#if defined(TARGET_MIPS64)
{
.name = "R4000",
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5 Petar Jovanovic
2014-02-03 23:55 ` Petar Jovanovic
@ 2014-02-08 3:34 ` Eric Johnson
2014-02-10 13:51 ` Andreas Färber
2 siblings, 0 replies; 19+ messages in thread
From: Eric Johnson @ 2014-02-08 3:34 UTC (permalink / raw)
To: Petar Jovanovic, qemu-devel@nongnu.org
Cc: Petar Jovanovic, aurelien@aurel32.net
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
________________________________________
From: qemu-devel-bounces+eric.johnson=imgtec.com@nongnu.org [qemu-devel-bounces+eric.johnson=imgtec.com@nongnu.org] on behalf of Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/mips-defs.h | 8 ++++++++
target-mips/translate_init.c | 25 +++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#define ISA_MIPS32R2 0x00000040
#define ISA_MIPS64 0x00000080
#define ISA_MIPS64R2 0x00000100
+#define ISA_MIPS32R3 0x00000200
+#define ISA_MIPS32R5 0x00000400
/* MIPS ASEs. */
#define ASE_MIPS16 0x00001000
@@ -64,6 +66,12 @@
#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
+/* MIPS Technologies "Release 3" */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies "Release 5" */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ /* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+ .name = "mips32r5-generic",
+ .CP0_PRid = 0x00019700,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#if defined(TARGET_MIPS64)
{
.name = "R4000",
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/4] target-mips: add support for CP0_Config4
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 2/4] target-mips: add support for CP0_Config4 Petar Jovanovic
@ 2014-02-08 3:35 ` Eric Johnson
0 siblings, 0 replies; 19+ messages in thread
From: Eric Johnson @ 2014-02-08 3:35 UTC (permalink / raw)
To: Petar Jovanovic, qemu-devel@nongnu.org
Cc: Petar Jovanovic, aurelien@aurel32.net
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
________________________________________
From: qemu-devel-bounces+eric.johnson=imgtec.com@nongnu.org [qemu-devel-bounces+eric.johnson=imgtec.com@nongnu.org] on behalf of Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v2 2/4] target-mips: add support for CP0_Config4
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Add CP0_Config4, define rw_bitmask.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/cpu.h | 3 +++
target-mips/helper.h | 1 +
target-mips/op_helper.c | 6 ++++++
target-mips/translate.c | 15 +++++++++++++--
target-mips/translate_init.c | 9 ++++++++-
5 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 9caf447..e8216ab 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -368,6 +368,9 @@ struct CPUMIPSState {
#define CP0C3_MT 2
#define CP0C3_SM 1
#define CP0C3_TL 0
+ uint32_t CP0_Config4;
+ uint32_t CP0_Config4_rw_bitmask;
+#define CP0C4_M 31
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 1a8b86d..9e4508b 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -134,6 +134,7 @@ DEF_HELPER_2(mtc0_ebase, void, env, tl)
DEF_HELPER_2(mttc0_ebase, void, env, tl)
DEF_HELPER_2(mtc0_config0, void, env, tl)
DEF_HELPER_2(mtc0_config2, void, env, tl)
+DEF_HELPER_2(mtc0_config4, void, env, tl)
DEF_HELPER_2(mtc0_lladdr, void, env, tl)
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 8e3a6d7..ed8dde8 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1489,6 +1489,12 @@ void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
}
+void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
+{
+ env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
+ (arg1 & env->CP0_Config4_rw_bitmask);
+}
+
void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
{
target_long mask = env->CP0_LLAddr_rw_bitmask;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index ef0a2c3..db2f430 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4405,7 +4405,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
rn = "Config3";
break;
- /* 4,5 are reserved */
+ case 4:
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
+ rn = "Config4";
+ break;
+ /* 5 is reserved */
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
@@ -4982,7 +4986,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* ignored, read only */
rn = "Config3";
break;
- /* 4,5 are reserved */
+ case 4:
+ gen_helper_mtc0_config4(cpu_env, arg);
+ rn = "Config4";
+ ctx->bstate = BS_STOP;
+ break;
+ /* 5 is reserved */
/* 6,7 are implementation dependent */
case 6:
/* ignored */
@@ -15916,6 +15925,8 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Config1 = env->cpu_model->CP0_Config1;
env->CP0_Config2 = env->cpu_model->CP0_Config2;
env->CP0_Config3 = env->cpu_model->CP0_Config3;
+ env->CP0_Config4 = env->cpu_model->CP0_Config4;
+ env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
env->CP0_Config6 = env->cpu_model->CP0_Config6;
env->CP0_Config7 = env->cpu_model->CP0_Config7;
env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index d74a0af..a0398cd 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -45,6 +45,9 @@
(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
(0 << CP0C3_SM) | (0 << CP0C3_TL))
+#define MIPS_CONFIG4 \
+((0 << CP0C4_M))
+
/* MMU types, the first four entries have the same layout as the
CP0C0_MT field. */
enum mips_mmu_types {
@@ -64,6 +67,8 @@ struct mips_def_t {
int32_t CP0_Config1;
int32_t CP0_Config2;
int32_t CP0_Config3;
+ int32_t CP0_Config4;
+ int32_t CP0_Config4_rw_bitmask;
int32_t CP0_Config6;
int32_t CP0_Config7;
target_ulong CP0_LLAddr_rw_bitmask;
@@ -345,7 +350,9 @@ static const mips_def_t mips_defs[] =
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),
+ .CP0_Config4 = MIPS_CONFIG4,
+ .CP0_Config4_rw_bitmask = 0,
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 3/4] target-mips: add support for CP0_Config5
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 3/4] target-mips: add support for CP0_Config5 Petar Jovanovic
@ 2014-02-08 3:35 ` Eric Johnson
0 siblings, 0 replies; 19+ messages in thread
From: Eric Johnson @ 2014-02-08 3:35 UTC (permalink / raw)
To: Petar Jovanovic, qemu-devel@nongnu.org
Cc: Petar Jovanovic, aurelien@aurel32.net
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
________________________________________
From: qemu-devel-bounces+eric.johnson=imgtec.com@nongnu.org [qemu-devel-bounces+eric.johnson=imgtec.com@nongnu.org] on behalf of Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v2 3/4] target-mips: add support for CP0_Config5
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/cpu.h | 10 ++++++++++
target-mips/helper.h | 1 +
target-mips/op_helper.c | 6 ++++++
target-mips/translate.c | 14 ++++++++++++--
target-mips/translate_init.c | 12 +++++++++++-
5 files changed, 40 insertions(+), 3 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index e8216ab..60c8061 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -73,6 +73,7 @@ struct CPUMIPSFPUContext {
float_status fp_status;
/* fpu implementation/revision register (fir) */
uint32_t fcr0;
+#define FCR0_UFRP 28
#define FCR0_F64 22
#define FCR0_L 21
#define FCR0_W 20
@@ -371,6 +372,15 @@ struct CPUMIPSState {
uint32_t CP0_Config4;
uint32_t CP0_Config4_rw_bitmask;
#define CP0C4_M 31
+ uint32_t CP0_Config5;
+ uint32_t CP0_Config5_rw_bitmask;
+#define CP0C5_M 31
+#define CP0C5_K 30
+#define CP0C5_CV 29
+#define CP0C5_EVA 28
+#define CP0C5_MSAEn 27
+#define CP0C5_UFR 2
+#define CP0C5_NFExists 0
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 9e4508b..b82f8e8 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -135,6 +135,7 @@ DEF_HELPER_2(mttc0_ebase, void, env, tl)
DEF_HELPER_2(mtc0_config0, void, env, tl)
DEF_HELPER_2(mtc0_config2, void, env, tl)
DEF_HELPER_2(mtc0_config4, void, env, tl)
+DEF_HELPER_2(mtc0_config5, void, env, tl)
DEF_HELPER_2(mtc0_lladdr, void, env, tl)
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index ed8dde8..eaf4d26 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1495,6 +1495,12 @@ void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
(arg1 & env->CP0_Config4_rw_bitmask);
}
+void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
+{
+ env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
+ (arg1 & env->CP0_Config5_rw_bitmask);
+}
+
void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
{
target_long mask = env->CP0_LLAddr_rw_bitmask;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index db2f430..02a90cb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4409,7 +4409,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
rn = "Config4";
break;
- /* 5 is reserved */
+ case 5:
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
+ rn = "Config5";
+ break;
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
@@ -4991,7 +4994,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "Config4";
ctx->bstate = BS_STOP;
break;
- /* 5 is reserved */
+ case 5:
+ gen_helper_mtc0_config5(cpu_env, arg);
+ rn = "Config5";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
+ break;
/* 6,7 are implementation dependent */
case 6:
/* ignored */
@@ -15927,6 +15935,8 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Config3 = env->cpu_model->CP0_Config3;
env->CP0_Config4 = env->cpu_model->CP0_Config4;
env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
+ env->CP0_Config5 = env->cpu_model->CP0_Config5;
+ env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
env->CP0_Config6 = env->cpu_model->CP0_Config6;
env->CP0_Config7 = env->cpu_model->CP0_Config7;
env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index a0398cd..3d4dc88 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -48,6 +48,9 @@
#define MIPS_CONFIG4 \
((0 << CP0C4_M))
+#define MIPS_CONFIG5 \
+((0 << CP0C5_M))
+
/* MMU types, the first four entries have the same layout as the
CP0C0_MT field. */
enum mips_mmu_types {
@@ -69,6 +72,8 @@ struct mips_def_t {
int32_t CP0_Config3;
int32_t CP0_Config4;
int32_t CP0_Config4_rw_bitmask;
+ int32_t CP0_Config5;
+ int32_t CP0_Config5_rw_bitmask;
int32_t CP0_Config6;
int32_t CP0_Config7;
target_ulong CP0_LLAddr_rw_bitmask;
@@ -351,8 +356,13 @@ static const mips_def_t mips_defs[] =
(1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),
- .CP0_Config4 = MIPS_CONFIG4,
+ .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
.CP0_Config4_rw_bitmask = 0,
+ .CP0_Config5 = MIPS_CONFIG5,
+ .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
+ (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
+ (1 << CP0C5_MSAEn) | (0 << CP0C5_UFR) |
+ (0 << CP0C5_NFExists),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 4/4] target-mips: add user-mode FR switch support for MIPS32r5
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 4/4] target-mips: add user-mode FR switch support for MIPS32r5 Petar Jovanovic
@ 2014-02-08 3:35 ` Eric Johnson
0 siblings, 0 replies; 19+ messages in thread
From: Eric Johnson @ 2014-02-08 3:35 UTC (permalink / raw)
To: Petar Jovanovic, qemu-devel@nongnu.org
Cc: Petar Jovanovic, aurelien@aurel32.net
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
________________________________________
From: qemu-devel-bounces+eric.johnson=imgtec.com@nongnu.org [qemu-devel-bounces+eric.johnson=imgtec.com@nongnu.org] on behalf of Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v2 4/4] target-mips: add user-mode FR switch support for MIPS32r5
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR.
helper_ctc1 has been extended with an additional parameter rt to check
requirements for UFR feature.
Definition of mips32r5-generic has been modified to include support for UFR.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/helper.h | 2 +-
target-mips/op_helper.c | 41 ++++++++++++++++++++++++++++++++++++++---
target-mips/translate.c | 14 ++++++++++++--
target-mips/translate_init.c | 9 +++++----
4 files changed, 56 insertions(+), 10 deletions(-)
diff --git a/target-mips/helper.h b/target-mips/helper.h
index b82f8e8..8c7921a 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -179,7 +179,7 @@ DEF_HELPER_2(yield, tl, env, tl)
/* CP1 functions */
DEF_HELPER_2(cfc1, tl, env, i32)
-DEF_HELPER_3(ctc1, void, env, tl, i32)
+DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
DEF_HELPER_2(float_cvtd_s, i64, env, i32)
DEF_HELPER_2(float_cvtd_w, i64, env, i32)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index eaf4d26..2ef6633 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2199,12 +2199,23 @@ static inline void restore_flush_mode(CPUMIPSState *env)
target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
{
- target_ulong arg1;
+ target_ulong arg1 = 0;
switch (reg) {
case 0:
arg1 = (int32_t)env->active_fpu.fcr0;
break;
+ case 1:
+ /* UFR Support - Read Status FR */
+ if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
+ if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
+ arg1 = (int32_t)
+ ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
+ } else {
+ helper_raise_exception(env, EXCP_RI);
+ }
+ }
+ break;
case 25:
arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
break;
@@ -2222,9 +2233,33 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
return arg1;
}
-void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
+void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
{
- switch(reg) {
+ switch (fs) {
+ case 1:
+ /* UFR Alias - Reset Status FR */
+ if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
+ return;
+ }
+ if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
+ env->CP0_Status &= ~(1 << CP0St_FR);
+ compute_hflags(env);
+ } else {
+ helper_raise_exception(env, EXCP_RI);
+ }
+ break;
+ case 4:
+ /* UNFR Alias - Set Status FR */
+ if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
+ return;
+ }
+ if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
+ env->CP0_Status |= (1 << CP0St_FR);
+ compute_hflags(env);
+ } else {
+ helper_raise_exception(env, EXCP_RI);
+ }
+ break;
case 25:
if (arg1 & 0xffffff00)
return;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 02a90cb..083f6ab 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -6818,7 +6818,12 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
break;
case 3:
/* XXX: For now we support only a single FPU context. */
- gen_helper_0e1i(ctc1, t0, rd);
+ {
+ TCGv_i32 fs_tmp = tcg_const_i32(rd);
+
+ gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
+ tcg_temp_free_i32(fs_tmp);
+ }
break;
/* COP2: Not implemented. */
case 4:
@@ -7254,7 +7259,12 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
break;
case OPC_CTC1:
gen_load_gpr(t0, rt);
- gen_helper_0e1i(ctc1, t0, fs);
+ {
+ TCGv_i32 fs_tmp = tcg_const_i32(fs);
+
+ gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
+ tcg_temp_free_i32(fs_tmp);
+ }
opn = "ctc1";
break;
#if defined(TARGET_MIPS64)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 3d4dc88..29d39e2 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -358,18 +358,19 @@ static const mips_def_t mips_defs[] =
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),
.CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
.CP0_Config4_rw_bitmask = 0,
- .CP0_Config5 = MIPS_CONFIG5,
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
.CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
(1 << CP0C5_CV) | (0 << CP0C5_EVA) |
- (1 << CP0C5_MSAEn) | (0 << CP0C5_UFR) |
+ (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
(0 << CP0C5_NFExists),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x3778FF1F,
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
- (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
+ (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x93 << FCR0_PRID),
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-02-04 13:59 ` Petar Jovanovic
@ 2014-02-10 11:21 ` Petar Jovanovic
2014-02-10 11:59 ` Peter Maydell
0 siblings, 1 reply; 19+ messages in thread
From: Petar Jovanovic @ 2014-02-10 11:21 UTC (permalink / raw)
To: Petar Jovanovic, qemu-devel@nongnu.org; +Cc: aurelien@aurel32.net
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
________________________________________
From: Petar Jovanovic
Sent: Tuesday, February 04, 2014 2:59 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: RE: [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
Regards,
Petar
________________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: Friday, January 24, 2014 5:18 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurelien@aurel32.net
Subject: [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
target-mips/mips-defs.h | 8 ++++++++
target-mips/translate_init.c | 25 +++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#define ISA_MIPS32R2 0x00000040
#define ISA_MIPS64 0x00000080
#define ISA_MIPS64R2 0x00000100
+#define ISA_MIPS32R3 0x00000200
+#define ISA_MIPS32R5 0x00000400
/* MIPS ASEs. */
#define ASE_MIPS16 0x00001000
@@ -64,6 +66,12 @@
#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
+/* MIPS Technologies "Release 3" */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies "Release 5" */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ /* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+ .name = "mips32r5-generic",
+ .CP0_PRid = 0x00019700,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#if defined(TARGET_MIPS64)
{
.name = "R4000",
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-02-10 11:21 ` Petar Jovanovic
@ 2014-02-10 11:59 ` Peter Maydell
0 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2014-02-10 11:59 UTC (permalink / raw)
To: Petar Jovanovic
Cc: Petar Jovanovic, aurelien@aurel32.net, qemu-devel@nongnu.org
On 10 February 2014 11:21, Petar Jovanovic <Petar.Jovanovic@imgtec.com> wrote:
> ping
> http://patchwork.ozlabs.org/patch/313937/
> http://patchwork.ozlabs.org/patch/313938/
> http://patchwork.ozlabs.org/patch/313944/
> http://patchwork.ozlabs.org/patch/313936/
These look reasonably sane to me on a quick glance.
So, in the interests of not stalling MIPS target development
indefinitely, I suggest you gather up these patches (and any
other small 'lost' MIPS patches which have got code review),
make sure they have the right Reviewed-by: and signed-off-by
tags on them, and put them into a pull request.
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5 Petar Jovanovic
2014-02-03 23:55 ` Petar Jovanovic
2014-02-08 3:34 ` Eric Johnson
@ 2014-02-10 13:51 ` Andreas Färber
2014-02-10 15:25 ` Petar Jovanovic
2014-02-10 15:42 ` Peter Maydell
2 siblings, 2 replies; 19+ messages in thread
From: Andreas Färber @ 2014-02-10 13:51 UTC (permalink / raw)
To: Petar Jovanovic, qemu-devel; +Cc: petar.jovanovic, aurelien
Am 24.01.2014 17:18, schrieb Petar Jovanovic:
> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
>
> Add mips32r5-generic among CPU definitions for MIPS.
> Define ISA_MIPS32R3 and ISA_MIPS32R5.
>
> Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
> ---
> target-mips/mips-defs.h | 8 ++++++++
> target-mips/translate_init.c | 25 +++++++++++++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
> index bf094a3..9dfa516 100644
> --- a/target-mips/mips-defs.h
> +++ b/target-mips/mips-defs.h
> @@ -29,6 +29,8 @@
> #define ISA_MIPS32R2 0x00000040
> #define ISA_MIPS64 0x00000080
> #define ISA_MIPS64R2 0x00000100
> +#define ISA_MIPS32R3 0x00000200
> +#define ISA_MIPS32R5 0x00000400
>
> /* MIPS ASEs. */
> #define ASE_MIPS16 0x00001000
> @@ -64,6 +66,12 @@
> #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
> #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
>
> +/* MIPS Technologies "Release 3" */
> +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
> +
> +/* MIPS Technologies "Release 5" */
> +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
> +
> /* Strictly follow the architecture standard:
> - Disallow "special" instruction handling for PMON/SPIM.
> Note that we still maintain Count/Compare to match the host clock. */
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index c45b1b2..d74a0af 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
> .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
> .mmu_type = MMU_TYPE_R4000,
> },
> + {
> + /* A generic CPU providing MIPS32 Release 5 features.
> + FIXME: Eventually this should be replaced by a real CPU model. */
That is not really possible. QEMU needs to keep command line backwards
compatibility, so if you add a generic model now, we will need to live
with the generic model for a long time. What's the difficulty with
taking "a real CPU model"? Is there no silicon yet or just a code name
rather than a marketing name?
Otherwise the patch looks okay.
Regards,
Andreas
P.S. If you want to ping a patch series, please ping the cover letter.
Sorry it's been taking so long, I'll provide my promised comments on the
KVM series right now...
> + .name = "mips32r5-generic",
> + .CP0_PRid = 0x00019700,
> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
> + (MMU_TYPE_R4000 << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
> + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
> + (1 << CP0C1_CA),
> + .CP0_Config2 = MIPS_CONFIG2,
> + .CP0_Config3 = MIPS_CONFIG3,
> + .CP0_LLAddr_rw_bitmask = 0,
> + .CP0_LLAddr_shift = 4,
> + .SYNCI_Step = 32,
> + .CCRes = 2,
> + .CP0_Status_rw_bitmask = 0x3778FF1F,
> + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
> + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
> + .SEGBITS = 32,
> + .PABITS = 32,
> + .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
> + .mmu_type = MMU_TYPE_R4000,
> + },
> #if defined(TARGET_MIPS64)
> {
> .name = "R4000",
>
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-02-10 13:51 ` Andreas Färber
@ 2014-02-10 15:25 ` Petar Jovanovic
2014-02-10 15:42 ` Peter Maydell
1 sibling, 0 replies; 19+ messages in thread
From: Petar Jovanovic @ 2014-02-10 15:25 UTC (permalink / raw)
To: Andreas Färber, Petar Jovanovic, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
> with the generic model for a long time. What's the difficulty with
> taking "a real CPU model"? Is there no silicon yet
No silicon available yet.
Regards,
Petar
________________________________________
From: Andreas Färber [afaerber@suse.de]
Sent: Monday, February 10, 2014 2:51 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
Am 24.01.2014 17:18, schrieb Petar Jovanovic:
> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
>
> Add mips32r5-generic among CPU definitions for MIPS.
> Define ISA_MIPS32R3 and ISA_MIPS32R5.
>
> Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
> ---
> target-mips/mips-defs.h | 8 ++++++++
> target-mips/translate_init.c | 25 +++++++++++++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
> index bf094a3..9dfa516 100644
> --- a/target-mips/mips-defs.h
> +++ b/target-mips/mips-defs.h
> @@ -29,6 +29,8 @@
> #define ISA_MIPS32R2 0x00000040
> #define ISA_MIPS64 0x00000080
> #define ISA_MIPS64R2 0x00000100
> +#define ISA_MIPS32R3 0x00000200
> +#define ISA_MIPS32R5 0x00000400
>
> /* MIPS ASEs. */
> #define ASE_MIPS16 0x00001000
> @@ -64,6 +66,12 @@
> #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
> #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
>
> +/* MIPS Technologies "Release 3" */
> +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
> +
> +/* MIPS Technologies "Release 5" */
> +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
> +
> /* Strictly follow the architecture standard:
> - Disallow "special" instruction handling for PMON/SPIM.
> Note that we still maintain Count/Compare to match the host clock. */
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index c45b1b2..d74a0af 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
> .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
> .mmu_type = MMU_TYPE_R4000,
> },
> + {
> + /* A generic CPU providing MIPS32 Release 5 features.
> + FIXME: Eventually this should be replaced by a real CPU model. */
That is not really possible. QEMU needs to keep command line backwards
compatibility, so if you add a generic model now, we will need to live
with the generic model for a long time. What's the difficulty with
taking "a real CPU model"? Is there no silicon yet or just a code name
rather than a marketing name?
Otherwise the patch looks okay.
Regards,
Andreas
P.S. If you want to ping a patch series, please ping the cover letter.
Sorry it's been taking so long, I'll provide my promised comments on the
KVM series right now...
> + .name = "mips32r5-generic",
> + .CP0_PRid = 0x00019700,
> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
> + (MMU_TYPE_R4000 << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
> + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
> + (1 << CP0C1_CA),
> + .CP0_Config2 = MIPS_CONFIG2,
> + .CP0_Config3 = MIPS_CONFIG3,
> + .CP0_LLAddr_rw_bitmask = 0,
> + .CP0_LLAddr_shift = 4,
> + .SYNCI_Step = 32,
> + .CCRes = 2,
> + .CP0_Status_rw_bitmask = 0x3778FF1F,
> + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
> + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
> + .SEGBITS = 32,
> + .PABITS = 32,
> + .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
> + .mmu_type = MMU_TYPE_R4000,
> + },
> #if defined(TARGET_MIPS64)
> {
> .name = "R4000",
>
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-02-10 13:51 ` Andreas Färber
2014-02-10 15:25 ` Petar Jovanovic
@ 2014-02-10 15:42 ` Peter Maydell
2014-02-13 14:51 ` Peter Maydell
1 sibling, 1 reply; 19+ messages in thread
From: Peter Maydell @ 2014-02-10 15:42 UTC (permalink / raw)
To: Andreas Färber
Cc: Petar Jovanovic, Petar Jovanovic, Aurelien Jarno, QEMU Developers
On 10 February 2014 13:51, Andreas Färber <afaerber@suse.de> wrote:
> Am 24.01.2014 17:18, schrieb Petar Jovanovic:
>> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
>> --- a/target-mips/translate_init.c
>> +++ b/target-mips/translate_init.c
>> @@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
>> .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
>> .mmu_type = MMU_TYPE_R4000,
>> },
>> + {
>> + /* A generic CPU providing MIPS32 Release 5 features.
>> + FIXME: Eventually this should be replaced by a real CPU model. */
>
> That is not really possible. QEMU needs to keep command line backwards
> compatibility, so if you add a generic model now, we will need to live
> with the generic model for a long time. What's the difficulty with
> taking "a real CPU model"? Is there no silicon yet or just a code name
> rather than a marketing name?
Good point, though I notice we have two MIPS CPUs already
with this same 'FIXME' comment about being generic.
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-02-10 15:42 ` Peter Maydell
@ 2014-02-13 14:51 ` Peter Maydell
2014-02-13 16:11 ` Andreas Färber
0 siblings, 1 reply; 19+ messages in thread
From: Peter Maydell @ 2014-02-13 14:51 UTC (permalink / raw)
To: Andreas Färber
Cc: Petar Jovanovic, Petar Jovanovic, Aurelien Jarno, QEMU Developers
On 10 February 2014 15:42, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 10 February 2014 13:51, Andreas Färber <afaerber@suse.de> wrote:
>> Am 24.01.2014 17:18, schrieb Petar Jovanovic:
>>> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
>>> --- a/target-mips/translate_init.c
>>> +++ b/target-mips/translate_init.c
>>> @@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
>>> .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
>>> .mmu_type = MMU_TYPE_R4000,
>>> },
>>> + {
>>> + /* A generic CPU providing MIPS32 Release 5 features.
>>> + FIXME: Eventually this should be replaced by a real CPU model. */
>>
>> That is not really possible. QEMU needs to keep command line backwards
>> compatibility, so if you add a generic model now, we will need to live
>> with the generic model for a long time. What's the difficulty with
>> taking "a real CPU model"? Is there no silicon yet or just a code name
>> rather than a marketing name?
>
> Good point, though I notice we have two MIPS CPUs already
> with this same 'FIXME' comment about being generic.
So before I apply the pull request with this patch, does
anybody want to actually object to adding another 'generic'
MIPS CPU to the two we have already? It seems reasonable
enough to me.
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-02-13 14:51 ` Peter Maydell
@ 2014-02-13 16:11 ` Andreas Färber
2014-02-13 16:27 ` Petar Jovanovic
0 siblings, 1 reply; 19+ messages in thread
From: Andreas Färber @ 2014-02-13 16:11 UTC (permalink / raw)
To: Peter Maydell, Petar Jovanovic
Cc: QEMU Developers, Aurelien Jarno, Petar Jovanovic
Am 13.02.2014 15:51, schrieb Peter Maydell:
> On 10 February 2014 15:42, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 10 February 2014 13:51, Andreas Färber <afaerber@suse.de> wrote:
>>> Am 24.01.2014 17:18, schrieb Petar Jovanovic:
>>>> From: Petar Jovanovic <petar.jovanovic@imgtec.com>
>>>> --- a/target-mips/translate_init.c
>>>> +++ b/target-mips/translate_init.c
>>>> @@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
>>>> .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
>>>> .mmu_type = MMU_TYPE_R4000,
>>>> },
>>>> + {
>>>> + /* A generic CPU providing MIPS32 Release 5 features.
>>>> + FIXME: Eventually this should be replaced by a real CPU model. */
>>>
>>> That is not really possible. QEMU needs to keep command line backwards
>>> compatibility, so if you add a generic model now, we will need to live
>>> with the generic model for a long time. What's the difficulty with
>>> taking "a real CPU model"? Is there no silicon yet or just a code name
>>> rather than a marketing name?
>>
>> Good point, though I notice we have two MIPS CPUs already
>> with this same 'FIXME' comment about being generic.
>
> So before I apply the pull request with this patch, does
> anybody want to actually object to adding another 'generic'
> MIPS CPU to the two we have already? It seems reasonable
> enough to me.
No objection from my side. I was however expecting Petar to drop the
FIXME in response to my reply, which I believe was still in the PULL.
Peter, are you planning (or did I miss) a follow-up cleaning that up,
whether for your new model or for all?
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
2014-02-13 16:11 ` Andreas Färber
@ 2014-02-13 16:27 ` Petar Jovanovic
0 siblings, 0 replies; 19+ messages in thread
From: Petar Jovanovic @ 2014-02-13 16:27 UTC (permalink / raw)
To: Andreas Färber, Peter Maydell, Petar Jovanovic
Cc: QEMU Developers, Aurelien Jarno
________________________________________
From: Andreas Färber [afaerber@suse.de]
Sent: Thursday, February 13, 2014 5:11 PM
To: Peter Maydell; Petar Jovanovic
Cc: QEMU Developers; Petar Jovanovic; Aurelien Jarno
Subject: Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
> No objection from my side. I was however expecting Petar to drop the
> FIXME in response to my reply, which I believe was still in the PULL.
> Peter, are you planning (or did I miss) a follow-up cleaning that up,
> whether for your new model or for all?
I would leave this FIXME, since we need to fix at least .CP0_PRid value
once the real silicon is available, because it will have to match value
known to kernel at that time.
As for other FIXMEs in the same file, I would change that in a separate
patch later.
I do plan to update this area more, with additional 5KEc and 5KEf
models.
Regards,
Petar
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2014-02-13 16:27 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-01-24 16:18 [Qemu-devel] [PATCH v2 0/4] mips32r5 with UFR Petar Jovanovic
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5 Petar Jovanovic
2014-02-03 23:55 ` Petar Jovanovic
2014-02-04 13:59 ` Petar Jovanovic
2014-02-10 11:21 ` Petar Jovanovic
2014-02-10 11:59 ` Peter Maydell
2014-02-08 3:34 ` Eric Johnson
2014-02-10 13:51 ` Andreas Färber
2014-02-10 15:25 ` Petar Jovanovic
2014-02-10 15:42 ` Peter Maydell
2014-02-13 14:51 ` Peter Maydell
2014-02-13 16:11 ` Andreas Färber
2014-02-13 16:27 ` Petar Jovanovic
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 2/4] target-mips: add support for CP0_Config4 Petar Jovanovic
2014-02-08 3:35 ` Eric Johnson
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 3/4] target-mips: add support for CP0_Config5 Petar Jovanovic
2014-02-08 3:35 ` Eric Johnson
2014-01-24 16:18 ` [Qemu-devel] [PATCH v2 4/4] target-mips: add user-mode FR switch support for MIPS32r5 Petar Jovanovic
2014-02-08 3:35 ` Eric Johnson
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