From: Richard Henderson <richard.henderson@linaro.org>
To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: philmd@redhat.com, bin.meng@windriver.com,
alistair.francis@wdc.com, palmer@dabbelt.com,
fabien.portas@grenoble-inp.org
Subject: Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions
Date: Mon, 15 Nov 2021 09:30:31 +0100 [thread overview]
Message-ID: <52a0a7b1-fa81-4428-1c0f-47a532716ef0@linaro.org> (raw)
In-Reply-To: <20211112145902.205131-11-frederic.petrot@univ-grenoble-alpes.fr>
On 11/12/21 3:58 PM, Frédéric Pétrot wrote:
> The 128-bit bitwise instructions do not need any function prototype change
> as the functions can be applied independently on the lower and upper part of
> the registers.
>
> Signed-off-by: Frédéric Pétrot<frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas<fabien.portas@grenoble-inp.org>
> ---
> target/riscv/translate.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-11-15 8:32 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 14:58 [PATCH v5 00/18] Adding partial support for 128-bit riscv target Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 01/18] exec/memop: Adding signedness to quad definitions Frédéric Pétrot
2021-11-14 12:49 ` Richard Henderson
2021-11-12 14:58 ` [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines Frédéric Pétrot
2021-11-15 8:01 ` Richard Henderson
2021-11-22 5:24 ` Alistair Francis
2021-11-24 7:22 ` Philippe Mathieu-Daudé
2021-11-12 14:58 ` [PATCH v5 03/18] qemu/int128: addition of div/rem 128-bit operations Frédéric Pétrot
2021-11-23 6:04 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 04/18] target/riscv: additional macros to check instruction support Frédéric Pétrot
2021-11-23 6:11 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers Frédéric Pétrot
2021-11-23 6:07 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot
2021-11-23 6:09 ` Alistair Francis
2021-11-23 10:58 ` Frédéric Pétrot
2021-11-23 11:09 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot
2021-11-24 6:12 ` Alistair Francis
2021-11-24 6:55 ` Frédéric Pétrot
2021-11-24 7:33 ` Philippe Mathieu-Daudé
2021-11-25 11:47 ` Alistair Francis
2021-11-25 14:44 ` Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 08/18] target/riscv: moving some insns close to similar insns Frédéric Pétrot
2021-11-23 6:10 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store Frédéric Pétrot
2021-11-15 8:29 ` Richard Henderson
2021-11-16 16:08 ` Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot
2021-11-15 8:30 ` Richard Henderson [this message]
2021-11-24 6:13 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot
2021-11-24 6:21 ` Alistair Francis
2021-11-12 14:58 ` [PATCH v5 12/18] target/riscv: support for 128-bit shift instructions Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 13/18] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 14/18] target/riscv: support for 128-bit M extension Frédéric Pétrot
2021-11-12 14:58 ` [PATCH v5 15/18] target/riscv: adding high part of some csrs Frédéric Pétrot
2021-11-24 6:22 ` Alistair Francis
2021-11-12 14:59 ` [PATCH v5 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot
2021-11-12 14:59 ` [PATCH v5 17/18] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot
2021-11-12 14:59 ` [PATCH v5 18/18] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot
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