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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id p1-20020a62b801000000b0050d5fc2cb7esm230225pfe.1.2022.04.28.08.33.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Apr 2022 08:33:15 -0700 (PDT) Message-ID: <52b52fdb-9419-bf44-8df7-a3a7ef477ab3@linaro.org> Date: Thu, 28 Apr 2022 08:33:14 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH 03/20] target/ppc: Substitute msr_pr macro with new M_MSR_PR macro Content-Language: en-US To: =?UTF-8?Q?V=c3=adctor_Colombo?= , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-devel@nongnu.org, qemu-ppc@nongnu.org References: <20220422185450.107256-1-victor.colombo@eldorado.org.br> <20220422185450.107256-4-victor.colombo@eldorado.org.br> <32cc9b8b-add7-a87c-3bb7-95e5c5707e3e@kaod.org> <9978cf74-2c81-98c8-d985-efe47d1519df@eldorado.org.br> From: Richard Henderson In-Reply-To: <9978cf74-2c81-98c8-d985-efe47d1519df@eldorado.org.br> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, groug@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/28/22 07:56, Víctor Colombo wrote: > A solution I could think that might be easy is: rename PPC_BIT to > PPC_BIT_ULL (behaves like BIT_ULL but 'inverted'), and create a new > PPC_BIT macro that just inverts the bit value > > #define PPC_BIT_ULL(bit) (0x8000000000000000ULL >> (bit)) > #define PPC_BIT(bit) (63 - (bit)) There's also room for a big-endian set of registerfield macros. (Don't forget s390x does the same thing, so "PPC" isn't appropriate generically.) Something like #define BE_FIELD_W(reg, field, regwidth, start, length) \ FIELD(reg, field, regwidth - start - length, length) #define BE_FIELD32(reg, field, start, length) \ BE_FIELD_(reg, field, 32, start, length) #define BE_FIELD64(reg, field, start, length) \ BE_FIELD_(reg, field, 64, start, length) at which point the usual FIELD_EX* and FIELD_DP* macros will work. r~