From: Richard Henderson <richard.henderson@linaro.org>
To: Ajeet Singh <itachis6234@gmail.com>, qemu-devel@nongnu.org
Cc: Warner Losh <imp@bsdimp.com>,
Mark Corbin <mark.corbin@embecsom.com>,
Ajeet Singh <itachis@FreeBSD.org>
Subject: Re: [PATCH 05/18] bsd-user: Add prototype for RISC-V TLS register setup
Date: Fri, 2 Aug 2024 23:04:56 +1000 [thread overview]
Message-ID: <52c62385-fdac-41ab-9117-093e11a2c72e@linaro.org> (raw)
In-Reply-To: <20240802083423.142365-6-itachis@FreeBSD.org>
On 8/2/24 18:34, Ajeet Singh wrote:
> From: Mark Corbin <mark.corbin@embecsom.com>
>
> Included the prototype for the 'target_cpu_set_tls' function in the
> 'target_arch.h' header file. This function is responsible for setting
> the Thread Local Storage (TLS) register for RISC-V architecture.
>
> Signed-off-by: Mark Corbin <mark.corbin@embecsom.com>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> ---
> bsd-user/riscv/target_arch.h | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
> create mode 100644 bsd-user/riscv/target_arch.h
>
> diff --git a/bsd-user/riscv/target_arch.h b/bsd-user/riscv/target_arch.h
> new file mode 100644
> index 0000000000..26ce07f343
> --- /dev/null
> +++ b/bsd-user/riscv/target_arch.h
> @@ -0,0 +1,27 @@
> +/*
> + * RISC-V specific prototypes
> + *
> + * Copyright (c) 2019 Mark Corbin <mark.corbin@embecsom.com>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef TARGET_ARCH_H
> +#define TARGET_ARCH_H
> +
> +#include "qemu.h"
> +
> +void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls);
> +
> +#endif /* TARGET_ARCH_H */
Really should be merged with the previous patch, which implements this function. But,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2024-08-02 13:05 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-02 8:34 [PATCH 00/18] bsd-user: Comprehensive RISCV support Ajeet Singh
2024-08-02 8:34 ` [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-08-02 12:41 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-08-02 12:54 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-08-02 12:58 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 04/18] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-08-02 13:01 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 05/18] bsd-user: Add prototype for " Ajeet Singh
2024-08-02 13:04 ` Richard Henderson [this message]
2024-08-02 8:34 ` [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-08-02 13:13 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 07/18] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-08-02 13:20 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 08/18] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-08-02 13:24 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 09/18] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-08-02 13:27 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 10/18] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-08-02 13:30 ` Richard Henderson
2024-08-03 0:05 ` Warner Losh
2024-08-02 8:34 ` [PATCH 11/18] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-08-02 13:33 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 12/18] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-08-02 13:35 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 13/18] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-08-02 13:35 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 14/18] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-08-02 13:38 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 15/18] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-08-02 13:46 ` Richard Henderson
2024-08-03 0:04 ` Warner Losh
2024-08-03 9:33 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 16/18] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-08-02 13:47 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 17/18] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-08-02 13:48 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 18/18] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
2024-08-02 13:50 ` Richard Henderson
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