From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:55813)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <lig.fnst@cn.fujitsu.com>) id 1WFbr4-0004aO-LV
	for qemu-devel@nongnu.org; Mon, 17 Feb 2014 23:00:28 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <lig.fnst@cn.fujitsu.com>) id 1WFbqy-0003TA-AC
	for qemu-devel@nongnu.org; Mon, 17 Feb 2014 23:00:22 -0500
Received: from [222.73.24.84] (port=60446 helo=song.cn.fujitsu.com)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <lig.fnst@cn.fujitsu.com>) id 1WFbqx-0003Rl-Os
	for qemu-devel@nongnu.org; Mon, 17 Feb 2014 23:00:16 -0500
Message-ID: <5302D8CE.5020502@cn.fujitsu.com>
Date: Tue, 18 Feb 2014 11:51:42 +0800
From: Li Guang <lig.fnst@cn.fujitsu.com>
MIME-Version: 1.0
References: <1392659003-8264-1-git-send-email-b.galvani@gmail.com>
	<1392659003-8264-5-git-send-email-b.galvani@gmail.com>
In-Reply-To: <1392659003-8264-5-git-send-email-b.galvani@gmail.com>
Content-Transfer-Encoding: 7bit
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Subject: Re: [Qemu-devel] [PATCH 4/7] allwinner-a10-pit: use level triggered
 interrupts
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Beniamino Galvani <b.galvani@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>, Peter Crosthwaite <peter.crosthwaite@xilinx.com>, qemu-devel@nongnu.org

Beniamino Galvani wrote:
> Converts the interrupt generation logic to the use of level triggered
> interrupts.
>
>    

any real difference, or block something?

> Signed-off-by: Beniamino Galvani<b.galvani@gmail.com>
> ---
>   hw/timer/allwinner-a10-pit.c |   13 ++++++++++++-
>   1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
> index 3e1c183..4723b25 100644
> --- a/hw/timer/allwinner-a10-pit.c
> +++ b/hw/timer/allwinner-a10-pit.c
> @@ -24,6 +24,15 @@ typedef struct TimerContext {
>       int index;
>   } TimerContext;
>
> +static void a10_pit_update_irq(AwA10PITState *s)
> +{
> +    int i;
> +
> +    for (i = 0; i<  AW_A10_PIT_TIMER_NR; i++) {
> +        qemu_set_irq(s->irq[i], s->irq_status&  s->irq_enable&  (1<<  i));
> +    }
> +}
> +
>   static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
>   {
>       AwA10PITState *s = AW_A10_PIT(opaque);
> @@ -79,9 +88,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
>       switch (offset) {
>       case AW_A10_PIT_TIMER_IRQ_EN:
>           s->irq_enable = value;
> +        a10_pit_update_irq(s);
>           break;
>       case AW_A10_PIT_TIMER_IRQ_ST:
>           s->irq_status&= ~value;
> +        a10_pit_update_irq(s);
>           break;
>       case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
>           index = offset&  0xf0;
> @@ -208,7 +219,7 @@ static void a10_pit_timer_cb(void *opaque)
>               ptimer_stop(s->timer[i]);
>               s->control[i]&= ~AW_A10_PIT_TIMER_EN;
>           }
> -        qemu_irq_pulse(s->irq[i]);
> +        a10_pit_update_irq(s);
>       }
>   }
>
>