From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56405) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WIDHV-0006Ht-EW for qemu-devel@nongnu.org; Tue, 25 Feb 2014 03:22:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WIDHQ-0002hV-G3 for qemu-devel@nongnu.org; Tue, 25 Feb 2014 03:22:25 -0500 Received: from mail-qc0-x22c.google.com ([2607:f8b0:400d:c01::22c]:44821) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WIDHQ-0002hK-BE for qemu-devel@nongnu.org; Tue, 25 Feb 2014 03:22:20 -0500 Received: by mail-qc0-f172.google.com with SMTP id w7so8342368qcr.31 for ; Tue, 25 Feb 2014 00:22:20 -0800 (PST) Sender: Paolo Bonzini Message-ID: <530C52B0.6070602@redhat.com> Date: Tue, 25 Feb 2014 09:22:08 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: <1393313432-15327-1-git-send-email-rth@twiddle.net> <1393313432-15327-3-git-send-email-rth@twiddle.net> In-Reply-To: <1393313432-15327-3-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/3] target-i386: Fix SSE status flag corruption List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org Il 25/02/2014 08:30, Richard Henderson ha scritto: > When we restore the mxcsr register with FXRSTOR, or set it with gdb, > we need to update the various SSE status flags in CPUX86State > > Reported-by: Richard Purdie > Signed-off-by: Richard Henderson > --- > Differs from Purdie's patch primarily in fixing gdb too. And that > required exporting update_sse_status. Which suggested that the name > and interface be changed to match the norm. > > > r~ > --- > target-i386/cpu.h | 3 +++ > target-i386/fpu_helper.c | 15 ++++++++------- > target-i386/gdbstub.c | 2 +- > 3 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index 1b94f0f..5d3f143 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -1259,6 +1259,9 @@ static inline void cpu_load_efer(CPUX86State *env, uint64_t val) > } > } > > +/* fpu_helper.c */ > +void cpu_set_mxcsr(CPUX86State *env, uint32_t val); > + > /* svm_helper.c */ > void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, > uint64_t param); > diff --git a/target-i386/fpu_helper.c b/target-i386/fpu_helper.c > index c0427fe..de7ba76 100644 > --- a/target-i386/fpu_helper.c > +++ b/target-i386/fpu_helper.c > @@ -1179,7 +1179,7 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64) > > if (env->cr[4] & CR4_OSFXSR_MASK) { > /* XXX: finish it */ > - env->mxcsr = cpu_ldl_data(env, ptr + 0x18); > + cpu_set_mxcsr(env, cpu_ldl_data(env, ptr + 0x18)); > /* cpu_ldl_data(env, ptr + 0x1c); */ > if (env->hflags & HF_CS64_MASK) { > nb_xmm_regs = 16; > @@ -1229,12 +1229,14 @@ floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper) > #define SSE_RC_CHOP 0x6000 > #define SSE_FZ 0x8000 > > -static void update_sse_status(CPUX86State *env) > +void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) > { > int rnd_type; > > + env->mxcsr = mxcsr; > + > /* set rounding mode */ > - switch (env->mxcsr & SSE_RC_MASK) { > + switch (mxcsr & SSE_RC_MASK) { > default: > case SSE_RC_NEAR: > rnd_type = float_round_nearest_even; > @@ -1252,16 +1254,15 @@ static void update_sse_status(CPUX86State *env) > set_float_rounding_mode(rnd_type, &env->sse_status); > > /* set denormals are zero */ > - set_flush_inputs_to_zero((env->mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status); > + set_flush_inputs_to_zero((mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status); > > /* set flush to zero */ > - set_flush_to_zero((env->mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status); > + set_flush_to_zero((mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status); > } > > void helper_ldmxcsr(CPUX86State *env, uint32_t val) > { > - env->mxcsr = val; > - update_sse_status(env); > + cpu_set_mxcsr(env, val); > } > > void helper_enter_mmx(CPUX86State *env) > diff --git a/target-i386/gdbstub.c b/target-i386/gdbstub.c > index 15bebef..d34e535 100644 > --- a/target-i386/gdbstub.c > +++ b/target-i386/gdbstub.c > @@ -222,7 +222,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) > return 4; > > case IDX_MXCSR_REG: > - env->mxcsr = ldl_p(mem_buf); > + cpu_set_mxcsr(env, ldl_p(mem_buf)); > return 4; > } > } > Reviewed-by: Paolo Bonzini