From: Richard Henderson <rth@twiddle.net>
To: Claudio Fontana <hw.claudio@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Claudio Fontana <claudio.fontana@huawei.com>,
Claudio Fontana <claudio.fontana@gmail.com>
Subject: Re: [Qemu-devel] [PATCH] tcg/aarch64: refactoring, remove inline magic insn numbers
Date: Fri, 28 Feb 2014 08:21:32 -0800 [thread overview]
Message-ID: <5310B78C.4050202@twiddle.net> (raw)
In-Reply-To: <CANv_3YbyJXb-BjNxVEmBbrMF3N698Aeuedo3Rb_qbvm2WyWa5A@mail.gmail.com>
On 02/28/2014 12:33 AM, Claudio Fontana wrote:
> ping?
>
> Richard, do you prefer to spin your polishing from last year instead?
I do prefer my patch set over this.
>> + INSN_IMM = 0x10000000, /* 3.4.1, 3.4.4 - add/sub and logical */
>> + INSN_SHIFT = 0x1ac02000, /* 3.5.8 - Data proc (2 source) */
...
>> +enum a64_insn_arith {
>> + ARITH_ADD = 0x01 << 24,
>> + ARITH_ADDS = 0x21 << 24,
>> + ARITH_SUB = 0x41 << 24,
>> + ARITH_SUBS = 0x61 << 24,
>> +
>> + ARITH_AND = 0x00 << 24,
>> + ARITH_OR = 0x20 << 24,
>> + ARITH_XOR = 0x40 << 24,
>> + ARITH_ANDS = 0x60 << 24,
>> };
...
>> +enum a64_insn_imm_arith { /* 3.4.1 */
>> + IMM_ADD = 0x01 << 24,
>> + IMM_ADDS = 0x21 << 24,
>> + IMM_SUB = 0x41 << 24,
>> + IMM_SUBS = 0x61 << 24
...
>> +enum a64_insn_imm_log { /* 3.4.4 */
>> + IMM_AND = 0x02 << 24,
>> + IMM_OR = 0x22 << 24,
>> + IMM_XOR = 0x42 << 24,
>> + IMM_ANDS = 0x62 << 24,
>> +};
In particular, I'm not keen on these opcode / subopcode splits. They just make
the source more confusing to read, and in my experience aren't helpful in
practice. It's just as easy to put them together into e.g. a single "ADDI" symbol.
r~
prev parent reply other threads:[~2014-02-28 16:21 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-07 18:17 [Qemu-devel] [PATCH] tcg/aarch64: refactoring, remove inline magic insn numbers Claudio Fontana
2014-02-28 8:33 ` Claudio Fontana
2014-02-28 16:21 ` Richard Henderson [this message]
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