From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34657) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WMbV8-0002Mp-AU for qemu-devel@nongnu.org; Sun, 09 Mar 2014 07:02:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WMbV4-0003E6-86 for qemu-devel@nongnu.org; Sun, 09 Mar 2014 07:02:38 -0400 Received: from host-82-135-62-35.customer.m-online.net ([82.135.62.35]:35150 helo=mail.embedded-brains.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WMbV3-0003DX-LB for qemu-devel@nongnu.org; Sun, 09 Mar 2014 07:02:34 -0400 Message-ID: <531C4A43.1030309@embedded-brains.de> Date: Sun, 09 Mar 2014 12:02:27 +0100 From: Sebastian Huber MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------050006050201010905010202" Subject: [Qemu-devel] [PATCH v5] target-sparc: Add and use CPU_FEATURE_CASA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, Mark Cave-Ayland , afaerber@suse.de, Fabien Chouteau This is a multi-part message in MIME format. --------------050006050201010905010202 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: quoted-printable The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will support this instruction for LEON3. GCC uses it to generate C11 atomic operations. The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is not defined use a supervisor data load/store for an ASI of 0x80 in helper_ld_asi()/helper_st_asi(). The supervisor data load/store was choosen according to the LEON3 documentation. The ASI 0x80 is defined in the SPARC V9 manual, Table 12=97Address Space Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted access, Primary address space. Tested with the following program: #include #include void test(void) { atomic_int a; int e; _Bool b; atomic_store(&a, 1); e =3D 1; b =3D atomic_compare_exchange_strong(&a, &e, 2); assert(b); assert(atomic_load(&a) =3D=3D 2); atomic_store(&a, 3); e =3D 4; b =3D atomic_compare_exchange_strong(&a, &e, 5); assert(!b); assert(atomic_load(&a) =3D=3D 3); } Tested also on a NGMP board with a LEON4 processor. Reviewed-by: Fabien Chouteau Reviewed-by: Andreas F=E4rber Signed-off-by: Sebastian Huber v4: Fix coding style. v5: Fix two typos. Generate an IU instead of FPU exception in case CASA=20 is not supported by the CPU. Define CASA feature for all SPARC64 CPUs=20 (due to the #ifndef TARGET_SPARC64 it must go into the #else branch). --=20 Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.huber@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine gesch=E4ftliche Mitteilung im Sinne des EHUG. --------------050006050201010905010202 Content-Type: text/x-patch; name="0001-target-sparc-Add-and-use-CPU_FEATURE_CASA.patch" Content-Disposition: attachment; filename*0="0001-target-sparc-Add-and-use-CPU_FEATURE_CASA.patch" Content-Transfer-Encoding: quoted-printable >>From ff5d7d85109111ccd65781ba5bc5fb437266e6dc Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 14 Feb 2014 17:06:52 +0100 Subject: [PATCH] target-sparc: Add and use CPU_FEATURE_CASA MIME-Version: 1.0 Content-Type: text/plain; charset=3DUTF-8 Content-Transfer-Encoding: 8bit The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will support this instruction for LEON3. GCC uses it to generate C11 atomic operations. The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is not defined use a supervisor data load/store for an ASI of 0x80 in helper_ld_asi()/helper_st_asi(). The supervisor data load/store was choosen according to the LEON3 documentation. The ASI 0x80 is defined in the SPARC V9 manual, Table 12=E2=80=94Address = Space Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted access, Primary address space. Tested with the following program: #include #include void test(void) { atomic_int a; int e; _Bool b; atomic_store(&a, 1); e =3D 1; b =3D atomic_compare_exchange_strong(&a, &e, 2); assert(b); assert(atomic_load(&a) =3D=3D 2); atomic_store(&a, 3); e =3D 4; b =3D atomic_compare_exchange_strong(&a, &e, 5); assert(!b); assert(atomic_load(&a) =3D=3D 3); } Tested also on a NGMP board with a LEON4 processor. Reviewed-by: Fabien Chouteau Reviewed-by: Andreas F=C3=A4rber Signed-off-by: Sebastian Huber --- target-sparc/cpu.c | 3 ++- target-sparc/cpu.h | 4 +++- target-sparc/helper.h | 4 +++- target-sparc/ldst_helper.c | 28 ++++++++++++++------------ target-sparc/translate.c | 49 ++++++++++++++++++++++++++++++----------= ------ 5 files changed, 56 insertions(+), 32 deletions(-) diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index e7f878e..5806e59 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -458,7 +458,8 @@ static const sparc_def_t sparc_defs[] =3D { .mmu_trcr_mask =3D 0xffffffff, .nwindows =3D 8, .features =3D CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | - CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDO= WN, + CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDO= WN | + CPU_FEATURE_CASA, }, #endif }; diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index c519063..ed6d2d1 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -271,6 +271,7 @@ typedef struct sparc_def_t { #define CPU_FEATURE_ASR17 (1 << 15) #define CPU_FEATURE_CACHE_CTRL (1 << 16) #define CPU_FEATURE_POWERDOWN (1 << 17) +#define CPU_FEATURE_CASA (1 << 18) =20 #ifndef TARGET_SPARC64 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ @@ -282,7 +283,8 @@ typedef struct sparc_def_t { CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ - CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD) + CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \ + CPU_FEATURE_CASA) enum { mmu_us_12, // Ultrasparc < III (64 entry TLB) mmu_us_3, // Ultrasparc III (512 entry TLB) diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 2a771b2..cd8d3fa 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -22,7 +22,6 @@ DEF_HELPER_1(popc, tl, tl) DEF_HELPER_4(ldda_asi, void, env, tl, int, int) DEF_HELPER_5(ldf_asi, void, env, tl, int, int, int) DEF_HELPER_5(stf_asi, void, env, tl, int, int, int) -DEF_HELPER_5(cas_asi, tl, env, tl, tl, tl, i32) DEF_HELPER_5(casx_asi, tl, env, tl, tl, tl, i32) DEF_HELPER_2(set_softint, void, env, i64) DEF_HELPER_2(clear_softint, void, env, i64) @@ -31,6 +30,9 @@ DEF_HELPER_2(tick_set_count, void, ptr, i64) DEF_HELPER_1(tick_get_count, i64, ptr) DEF_HELPER_2(tick_set_limit, void, ptr, i64) #endif +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) +DEF_HELPER_5(cas_asi, tl, env, tl, tl, tl, i32) +#endif DEF_HELPER_3(check_align, void, env, tl, i32) DEF_HELPER_1(debug, void, env) DEF_HELPER_1(save, void, env) diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 92761ad..32491b4 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -584,6 +584,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulo= ng addr, int asi, int size, } break; case 0xb: /* Supervisor data access */ + case 0x80: switch (size) { case 1: ret =3D cpu_ldub_kernel(env, addr); @@ -955,6 +956,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, uint64_t val, int asi, } break; case 0xb: /* Supervisor data access */ + case 0x80: switch (size) { case 1: cpu_stb_kernel(env, addr, val); @@ -2232,33 +2234,35 @@ void helper_stf_asi(CPUSPARCState *env, target_ul= ong addr, int asi, int size, } } =20 -target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr, - target_ulong val1, target_ulong val2, uint32= _t asi) +target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr, + target_ulong val1, target_ulong val2, + uint32_t asi) { target_ulong ret; =20 - val2 &=3D 0xffffffffUL; - ret =3D helper_ld_asi(env, addr, asi, 4, 0); - ret &=3D 0xffffffffUL; + ret =3D helper_ld_asi(env, addr, asi, 8, 0); if (val2 =3D=3D ret) { - helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4); + helper_st_asi(env, addr, val1, asi, 8); } return ret; } +#endif /* TARGET_SPARC64 */ =20 -target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr, - target_ulong val1, target_ulong val2, - uint32_t asi) +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) +target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr, + target_ulong val1, target_ulong val2, uint32= _t asi) { target_ulong ret; =20 - ret =3D helper_ld_asi(env, addr, asi, 8, 0); + val2 &=3D 0xffffffffUL; + ret =3D helper_ld_asi(env, addr, asi, 4, 0); + ret &=3D 0xffffffffUL; if (val2 =3D=3D ret) { - helper_st_asi(env, addr, val1, asi, 8); + helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4); } return ret; } -#endif /* TARGET_SPARC64 */ +#endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */ =20 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx) { diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 6150b22..1d857a3 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2107,18 +2107,6 @@ static inline void gen_stda_asi(DisasContext *dc, = TCGv hi, TCGv addr, tcg_temp_free_i64(t64); } =20 -static inline void gen_cas_asi(DisasContext *dc, TCGv addr, - TCGv val2, int insn, int rd) -{ - TCGv val1 =3D gen_load_gpr(dc, rd); - TCGv dst =3D gen_dest_gpr(dc, rd); - TCGv_i32 r_asi =3D gen_get_asi(insn, addr); - - gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi); - tcg_temp_free_i32(r_asi); - gen_store_gpr(dc, rd, dst); -} - static inline void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2, int insn, int rd) { @@ -2229,6 +2217,22 @@ static inline void gen_stda_asi(DisasContext *dc, = TCGv hi, TCGv addr, #endif =20 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) +static inline void gen_cas_asi(DisasContext *dc, TCGv addr, + TCGv val2, int insn, int rd) +{ + TCGv val1 =3D gen_load_gpr(dc, rd); + TCGv dst =3D gen_dest_gpr(dc, rd); +#ifdef TARGET_SPARC64 + TCGv_i32 r_asi =3D gen_get_asi(insn, addr); +#else + TCGv_i32 r_asi =3D tcg_const_i32(GET_FIELD(insn, 19, 26)); +#endif + + gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi); + tcg_temp_free_i32(r_asi); + gen_store_gpr(dc, rd, dst); +} + static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) { TCGv_i64 r_val; @@ -5103,11 +5107,6 @@ static void disas_sparc_insn(DisasContext * dc, un= signed int insn) } gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); break; - case 0x3c: /* V9 casa */ - rs2 =3D GET_FIELD(insn, 27, 31); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); - break; case 0x3e: /* V9 casxa */ rs2 =3D GET_FIELD(insn, 27, 31); cpu_src2 =3D gen_load_gpr(dc, rs2); @@ -5120,6 +5119,22 @@ static void disas_sparc_insn(DisasContext * dc, un= signed int insn) case 0x37: /* stdc */ goto ncp_insn; #endif +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) + case 0x3c: /* V9 or LEON3 casa */ + CHECK_IU_FEATURE(dc, CASA); +#ifndef TARGET_SPARC64 + if (IS_IMM) { + goto illegal_insn; + } + if (!supervisor(dc)) { + goto priv_insn; + } +#endif + rs2 =3D GET_FIELD(insn, 27, 31); + cpu_src2 =3D gen_load_gpr(dc, rs2); + gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); + break; +#endif default: goto illegal_insn; } --=20 1.8.1.4 --------------050006050201010905010202--