* [Qemu-devel] [PATCH v5] target-sparc: Add and use CPU_FEATURE_CASA
@ 2014-03-09 11:02 Sebastian Huber
2014-03-09 21:57 ` Mark Cave-Ayland
2014-03-10 20:48 ` Richard Henderson
0 siblings, 2 replies; 3+ messages in thread
From: Sebastian Huber @ 2014-03-09 11:02 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Mark Cave-Ayland, afaerber, Fabien Chouteau
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The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9 will support this instruction for LEON3. GCC uses it to
generate C11 atomic operations.
The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is
not defined use a supervisor data load/store for an ASI of 0x80 in
helper_ld_asi()/helper_st_asi(). The supervisor data load/store was
choosen according to the LEON3 documentation.
The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space
Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted
access, Primary address space.
Tested with the following program:
#include <assert.h>
#include <stdatomic.h>
void test(void)
{
atomic_int a;
int e;
_Bool b;
atomic_store(&a, 1);
e = 1;
b = atomic_compare_exchange_strong(&a, &e, 2);
assert(b);
assert(atomic_load(&a) == 2);
atomic_store(&a, 3);
e = 4;
b = atomic_compare_exchange_strong(&a, &e, 5);
assert(!b);
assert(atomic_load(&a) == 3);
}
Tested also on a NGMP board with a LEON4 processor.
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
v4: Fix coding style.
v5: Fix two typos. Generate an IU instead of FPU exception in case CASA
is not supported by the CPU. Define CASA feature for all SPARC64 CPUs
(due to the #ifndef TARGET_SPARC64 it must go into the #else branch).
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.huber@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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>From ff5d7d85109111ccd65781ba5bc5fb437266e6dc Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 14 Feb 2014 17:06:52 +0100
Subject: [PATCH] target-sparc: Add and use CPU_FEATURE_CASA
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9 will support this instruction for LEON3. GCC uses it to
generate C11 atomic operations.
The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is
not defined use a supervisor data load/store for an ASI of 0x80 in
helper_ld_asi()/helper_st_asi(). The supervisor data load/store was
choosen according to the LEON3 documentation.
The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space
Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted
access, Primary address space.
Tested with the following program:
#include <assert.h>
#include <stdatomic.h>
void test(void)
{
atomic_int a;
int e;
_Bool b;
atomic_store(&a, 1);
e = 1;
b = atomic_compare_exchange_strong(&a, &e, 2);
assert(b);
assert(atomic_load(&a) == 2);
atomic_store(&a, 3);
e = 4;
b = atomic_compare_exchange_strong(&a, &e, 5);
assert(!b);
assert(atomic_load(&a) == 3);
}
Tested also on a NGMP board with a LEON4 processor.
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
target-sparc/cpu.c | 3 ++-
target-sparc/cpu.h | 4 +++-
target-sparc/helper.h | 4 +++-
target-sparc/ldst_helper.c | 28 ++++++++++++++------------
target-sparc/translate.c | 49 ++++++++++++++++++++++++++++++----------------
5 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index e7f878e..5806e59 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -458,7 +458,8 @@ static const sparc_def_t sparc_defs[] = {
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
- CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN,
+ CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
+ CPU_FEATURE_CASA,
},
#endif
};
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index c519063..ed6d2d1 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -271,6 +271,7 @@ typedef struct sparc_def_t {
#define CPU_FEATURE_ASR17 (1 << 15)
#define CPU_FEATURE_CACHE_CTRL (1 << 16)
#define CPU_FEATURE_POWERDOWN (1 << 17)
+#define CPU_FEATURE_CASA (1 << 18)
#ifndef TARGET_SPARC64
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
@@ -282,7 +283,8 @@ typedef struct sparc_def_t {
CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
- CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
+ CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
+ CPU_FEATURE_CASA)
enum {
mmu_us_12, // Ultrasparc < III (64 entry TLB)
mmu_us_3, // Ultrasparc III (512 entry TLB)
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index 2a771b2..cd8d3fa 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -22,7 +22,6 @@ DEF_HELPER_1(popc, tl, tl)
DEF_HELPER_4(ldda_asi, void, env, tl, int, int)
DEF_HELPER_5(ldf_asi, void, env, tl, int, int, int)
DEF_HELPER_5(stf_asi, void, env, tl, int, int, int)
-DEF_HELPER_5(cas_asi, tl, env, tl, tl, tl, i32)
DEF_HELPER_5(casx_asi, tl, env, tl, tl, tl, i32)
DEF_HELPER_2(set_softint, void, env, i64)
DEF_HELPER_2(clear_softint, void, env, i64)
@@ -31,6 +30,9 @@ DEF_HELPER_2(tick_set_count, void, ptr, i64)
DEF_HELPER_1(tick_get_count, i64, ptr)
DEF_HELPER_2(tick_set_limit, void, ptr, i64)
#endif
+#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+DEF_HELPER_5(cas_asi, tl, env, tl, tl, tl, i32)
+#endif
DEF_HELPER_3(check_align, void, env, tl, i32)
DEF_HELPER_1(debug, void, env)
DEF_HELPER_1(save, void, env)
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 92761ad..32491b4 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -584,6 +584,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
}
break;
case 0xb: /* Supervisor data access */
+ case 0x80:
switch (size) {
case 1:
ret = cpu_ldub_kernel(env, addr);
@@ -955,6 +956,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
}
break;
case 0xb: /* Supervisor data access */
+ case 0x80:
switch (size) {
case 1:
cpu_stb_kernel(env, addr, val);
@@ -2232,33 +2234,35 @@ void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
}
}
-target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
- target_ulong val1, target_ulong val2, uint32_t asi)
+target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
+ target_ulong val1, target_ulong val2,
+ uint32_t asi)
{
target_ulong ret;
- val2 &= 0xffffffffUL;
- ret = helper_ld_asi(env, addr, asi, 4, 0);
- ret &= 0xffffffffUL;
+ ret = helper_ld_asi(env, addr, asi, 8, 0);
if (val2 == ret) {
- helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
+ helper_st_asi(env, addr, val1, asi, 8);
}
return ret;
}
+#endif /* TARGET_SPARC64 */
-target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
- target_ulong val1, target_ulong val2,
- uint32_t asi)
+#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
+ target_ulong val1, target_ulong val2, uint32_t asi)
{
target_ulong ret;
- ret = helper_ld_asi(env, addr, asi, 8, 0);
+ val2 &= 0xffffffffUL;
+ ret = helper_ld_asi(env, addr, asi, 4, 0);
+ ret &= 0xffffffffUL;
if (val2 == ret) {
- helper_st_asi(env, addr, val1, asi, 8);
+ helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
}
return ret;
}
-#endif /* TARGET_SPARC64 */
+#endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
{
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 6150b22..1d857a3 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2107,18 +2107,6 @@ static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
tcg_temp_free_i64(t64);
}
-static inline void gen_cas_asi(DisasContext *dc, TCGv addr,
- TCGv val2, int insn, int rd)
-{
- TCGv val1 = gen_load_gpr(dc, rd);
- TCGv dst = gen_dest_gpr(dc, rd);
- TCGv_i32 r_asi = gen_get_asi(insn, addr);
-
- gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
- tcg_temp_free_i32(r_asi);
- gen_store_gpr(dc, rd, dst);
-}
-
static inline void gen_casx_asi(DisasContext *dc, TCGv addr,
TCGv val2, int insn, int rd)
{
@@ -2229,6 +2217,22 @@ static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
#endif
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+static inline void gen_cas_asi(DisasContext *dc, TCGv addr,
+ TCGv val2, int insn, int rd)
+{
+ TCGv val1 = gen_load_gpr(dc, rd);
+ TCGv dst = gen_dest_gpr(dc, rd);
+#ifdef TARGET_SPARC64
+ TCGv_i32 r_asi = gen_get_asi(insn, addr);
+#else
+ TCGv_i32 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
+#endif
+
+ gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
+ tcg_temp_free_i32(r_asi);
+ gen_store_gpr(dc, rd, dst);
+}
+
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
{
TCGv_i64 r_val;
@@ -5103,11 +5107,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
break;
- case 0x3c: /* V9 casa */
- rs2 = GET_FIELD(insn, 27, 31);
- cpu_src2 = gen_load_gpr(dc, rs2);
- gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
- break;
case 0x3e: /* V9 casxa */
rs2 = GET_FIELD(insn, 27, 31);
cpu_src2 = gen_load_gpr(dc, rs2);
@@ -5120,6 +5119,22 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x37: /* stdc */
goto ncp_insn;
#endif
+#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+ case 0x3c: /* V9 or LEON3 casa */
+ CHECK_IU_FEATURE(dc, CASA);
+#ifndef TARGET_SPARC64
+ if (IS_IMM) {
+ goto illegal_insn;
+ }
+ if (!supervisor(dc)) {
+ goto priv_insn;
+ }
+#endif
+ rs2 = GET_FIELD(insn, 27, 31);
+ cpu_src2 = gen_load_gpr(dc, rs2);
+ gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
+ break;
+#endif
default:
goto illegal_insn;
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH v5] target-sparc: Add and use CPU_FEATURE_CASA
2014-03-09 11:02 [Qemu-devel] [PATCH v5] target-sparc: Add and use CPU_FEATURE_CASA Sebastian Huber
@ 2014-03-09 21:57 ` Mark Cave-Ayland
2014-03-10 20:48 ` Richard Henderson
1 sibling, 0 replies; 3+ messages in thread
From: Mark Cave-Ayland @ 2014-03-09 21:57 UTC (permalink / raw)
To: Sebastian Huber; +Cc: blauwirbel, rth, qemu-devel, Fabien Chouteau, afaerber
On 09/03/14 11:02, Sebastian Huber wrote:
> The LEON3 processor has support for the CASA instruction which is
> normally only available for SPARC V9 processors. Binutils 2.24
> and GCC 4.9 will support this instruction for LEON3. GCC uses it to
> generate C11 atomic operations.
>
> The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is
> not defined use a supervisor data load/store for an ASI of 0x80 in
> helper_ld_asi()/helper_st_asi(). The supervisor data load/store was
> choosen according to the LEON3 documentation.
>
> The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space
> Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted
> access, Primary address space.
>
> Tested with the following program:
>
> #include <assert.h>
> #include <stdatomic.h>
>
> void test(void)
> {
> atomic_int a;
> int e;
> _Bool b;
>
> atomic_store(&a, 1);
> e = 1;
> b = atomic_compare_exchange_strong(&a, &e, 2);
> assert(b);
> assert(atomic_load(&a) == 2);
>
> atomic_store(&a, 3);
> e = 4;
> b = atomic_compare_exchange_strong(&a, &e, 5);
> assert(!b);
> assert(atomic_load(&a) == 3);
> }
>
> Tested also on a NGMP board with a LEON4 processor.
>
> Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
> Reviewed-by: Andreas Färber <afaerber@suse.de>
> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
>
> v4: Fix coding style.
>
> v5: Fix two typos. Generate an IU instead of FPU exception in case CASA
> is not supported by the CPU. Define CASA feature for all SPARC64 CPUs
> (due to the #ifndef TARGET_SPARC64 it must go into the #else branch).
This version of the patch passes all of my tests on SPARC32 and SPARC64 so:
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
If someone like Richard (added as CC) could give the TCG parts a quick
sanity check then given the length of time this patch has been around
(and Sebastian's responsiveness) then I'd be okay for this patch to be
included in 2.0.
ATB,
Mark.
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH v5] target-sparc: Add and use CPU_FEATURE_CASA
2014-03-09 11:02 [Qemu-devel] [PATCH v5] target-sparc: Add and use CPU_FEATURE_CASA Sebastian Huber
2014-03-09 21:57 ` Mark Cave-Ayland
@ 2014-03-10 20:48 ` Richard Henderson
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2014-03-10 20:48 UTC (permalink / raw)
To: Sebastian Huber, qemu-devel
Cc: blauwirbel, Mark Cave-Ayland, afaerber, Fabien Chouteau
On 03/09/2014 04:02 AM, Sebastian Huber wrote:
> #endif
> +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
> + case 0x3c: /* V9 or LEON3 casa */
> + CHECK_IU_FEATURE(dc, CASA);
> +#ifndef TARGET_SPARC64
> + if (IS_IMM) {
> + goto illegal_insn;
> + }
> + if (!supervisor(dc)) {
> + goto priv_insn;
> + }
> +#endif
> + rs2 = GET_FIELD(insn, 27, 31);
> + cpu_src2 = gen_load_gpr(dc, rs2);
> + gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
> + break;
> +#endif
Might as well put the feature check inside the ifndef sparc64,
since we know that sparc64 always has the feature.
Otherwise,
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-03-09 11:02 [Qemu-devel] [PATCH v5] target-sparc: Add and use CPU_FEATURE_CASA Sebastian Huber
2014-03-09 21:57 ` Mark Cave-Ayland
2014-03-10 20:48 ` Richard Henderson
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