From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48822) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WMgRs-0006lu-Mz for qemu-devel@nongnu.org; Sun, 09 Mar 2014 12:19:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WMgRo-0006y5-9R for qemu-devel@nongnu.org; Sun, 09 Mar 2014 12:19:36 -0400 Received: from cantor2.suse.de ([195.135.220.15]:36198 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WMgRo-0006y0-3I for qemu-devel@nongnu.org; Sun, 09 Mar 2014 12:19:32 -0400 Message-ID: <531C9491.8060207@suse.de> Date: Sun, 09 Mar 2014 17:19:29 +0100 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1393901749-5944-1-git-send-email-afaerber@suse.de> <53163862.7080109@suse.de> <531B828A.4090103@ilande.co.uk> In-Reply-To: <531B828A.4090103@ilande.co.uk> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH qom-cpu 0/6] cpu: Unifying features parsing List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Cave-Ayland Cc: Peter Maydell , Eduardo Habkost , Alexey Kardashevskiy , Sebastian Huber , qemu-devel@nongnu.org, Fabien Chouteau , Anthony Liguori , Igor Mammedov Am 08.03.2014 21:50, schrieb Mark Cave-Ayland: > On 04/03/14 20:32, Andreas F=C3=A4rber wrote: >=20 >> Am 04.03.2014 03:55, schrieb Andreas F=C3=A4rber: >>> Hello, >>> >>> Prompted by Alexey's desire for tweakable PowerPCCPU properties but >>> also by >>> Peter's wish for ARMCPU properties, this series sets out to align >>> cpu_model >>> parsing across targets. >>> >>> QemuOpts would've been nice to use, but on the one hand x86 and sparc >>> use >>> QemuOpts-incompatible +foo and -foo syntax (which accumulate rather >>> than apply >>> immediately) and on the other linux-user and bsd-user don't use >>> QemuOpts at all. >>> >>> The x86 implementation is closest to the proposed API, save for some >>> laziness. >>> SPARC is brought in line. And as fallback for the remaining targets a >>> new >>> implementation, derived from x86 but supporting only key=3Dvalue >>> format, is added. >>> >>> To facilitate using this infrastructure, a generic CPU init function >>> is created. >>> >>> Only lightly tested. Available at: >>> git://github.com/afaerber/qemu-cpu.git qom-cpu-features.v1 >>> https://github.com/afaerber/qemu-cpu/commits/qom-cpu-features.v1 >>> >>> Regards, >>> Andreas >>> >>> Cc: Alexey Kardashevskiy >>> Cc: Peter Maydell >>> Cc: Anthony Liguori >>> >>> Andreas F=C3=A4rber (6): >>> cpu: Introduce CPUClass::parse_features() hook >>> target-sparc: Use error_report() for CPU error reporting >>> target-sparc: Implement CPUClass::parse_features() for SPARCCPU >>> target-sparc: Defer SPARCCPU feature inference to QOM realize >> >> Mark and Fabien, forgot to CC you: Could you take a look at the sparc >> parts and give them some testing please? >> >> The very latest version can be found on qom-cpu-ppc branch if necessar= y. >> >> Thanks, >> Andreas >=20 > Hi Andreas, >=20 > I've had a quick test of this branch, and while I don't tend to use CPU > options that much, the parsing seems to work as I might expect from > looking at the changes. I think any other snags if they exist can be > picked up during pre-release testing so: >=20 > Tested-by: Mark Cave-Ayland Thanks a lot, proceeding to staging it on qom-cpu-next: https://github.com/afaerber/qemu-cpu/commits/qom-cpu-next Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg